Abstract: In a process for preparing p-dichlorobenzene by nuclear chlorination of benzene and/or chlorobenzene as the starting material with chlorine molecules, chlorination is carried out using aluminum chloride in an amount of 0.1–3 millimols per mol of the starting material and phenothiazines such as 10H-phenothiazine-10-carboxylic acid phenyl ester in an amount of 0.1–0.9 mols per mol of aluminum chloride so as to be a chlorination degree in a range of 1.2–2.5, by which p-dichlorobenzene can be obtained in a high para-selectivity and a short reaction time.

Abstract: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.

Abstract: A semiconductor memory device includes memory cell arrays, a redundancy cell array shared by the memory cell arrays, a correction capacitance, and switching circuits arranged in correspondence with the memory cell arrays. Each memory cell array includes ferroelectric cells arranged at the intersections between word lines and bit lines. The redundancy cell array includes spare ferroelectric cells arranged at the intersections between spare word lines and redundancy bit lines. The number of spare ferroelectric cells connected to the redundancy bit line is smaller than that of ferroelectric cells connected to the bit line in each memory cell array. The correction capacitance is connected to the redundancy bit line to make its capacitance equivalent to that of the bit line. When a replaced ferroelectric cell in the memory cell array is selected, the switching circuits select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

Abstract: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.

Abstract: In a process for preparing p-dichlorobenzene by nuclear chlorination of benzene and/or chlorobenzene as the starting material with chlorine molecules, chlorination is carried out using aluminum chloride in an amount of 0.1-3 millimols per mol of the starting material and phenothiazines such as 10H-phenothiazine-10-carboxylic acid phenyl ester in an amount of 0.1-0.9 mols per mol of aluminum chloride so as to be a chlorination degree in a range of 1.2-2.5, by which p-dichlorobenzene can be obtained in a high para-selectivity and a short reaction time.

Abstract: A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.

Abstract: An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected to terminals of the cell transistor. The word line selecting circuit successively selects the word lines connected to the cell transistors in the memory cells in the memory cell block in response to address signals successively input from an outside of the device, during an active cycle. The driving circuit applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are successively selected by the word line selecting circuit.

Abstract: A semiconductor memory device includes memory cell arrays, a redundancy cell array shared by the memory cell arrays, a correction capacitance, and switching circuits arranged in correspondence with the memory cell arrays. Each memory cell array includes ferroelectric cells arranged at the intersections between word lines and bit lines. The redundancy cell array includes spare ferroelectric cells arranged at the intersections between spare word lines and redundancy bit lines. The number of spare ferroelectric cells connected to the redundancy bit line is smaller than that of ferroelectric cells connected to the bit line in each memory cell array. The correction capacitance is connected to the redundancy bit line to make its capacitance equivalent to that of the bit line. When a replaced ferroelectric cell in the memory cell array is selected, the switching circuits select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

Abstract: A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.

Abstract: A redundancy unit comprising first and second fuse blocks for programming the redundancy element is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits connected to the plurality of input/output terminals. The switch circuits simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of input/output terminals to input cell data written to the memory cell array and output cell data read from the memory cell array, a test mode setting circuit which sets a test mode to monitor a plurality of timing signals which control input/output operation timing of the cell data, and switch circuits connected to the plurality of input/output terminals. The switch circuits simultaneously output the plurality of timing signals from the plurality of input/output terminals in the test mode.

Abstract: Disclosed are a printing color management system and a printing color management method, wherein a plurality of machine plates, which is associated with a plurality of monochromatic images wherein a color image is color-separated, is created in accordance with image data, and an color image is created in such a manner that the plurality of machine plates is used to sequentially print a plurality of monochromatic images on an overlapping basis. The printing color management system and the printing color management method are capable of creating a printed image closely similar in color to a target printed matter, while an image quality of the printed image is guaranteed.

Abstract: In a semiconductor apparatus, the first voltage detection circuit is configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher. The second voltage detection circuit is configured to judge whether the potential of the input signal is higher or lower than a second reference potential, and output a second level signal if the potential of the input signal is judged to be lower. The operation mode entry setting circuit is configured to judge plural times whether or not output signals from the first and second voltage detection circuits coincide with predetermined levels in synchronization with an input clock signal, and make an enter of an operation mode if all of the judged-results show that the output signals coincide with the predetermined levels.

Abstract: In a semiconductor memory device, a plurality of memory cells is coupled in series to form a memory cell block, which data is read out and data is written in, each memory cell having a cell transistor for selecting the memory cell and a ferroelectric capacitor coupled between a source and a drain of the cell transistor. The word line is coupled to a gate of the cell transistor. The memory cell block selection transistor is coupled to one terminal of the memory cell block of the plurality of memory cells. The bit line is coupled to the memory cell block selection transistor. The plate line is coupled to the other terminal of the memory cell block of the plurality of memory cells. The word line control circuit controls the word line to keep the cell transistor selected even after the memory cell block selection transistor is turned off.

Abstract: In a semiconductor memory device, a plurality of memory cells is coupled in series to form a memory cell block, which data is read out and data is written in, each memory cell having a cell transistor for selecting the memory cell and a ferroelectric capacitor coupled between a source and a drain of the cell transistor. The word line is coupled to a gate of the cell transistor. The memory cell block selection transistor is coupled to one terminal of the memory cell block of the plurality of memory cells. The bit line is coupled to the memory cell block selection transistor. The plate line is coupled to the other terminal of the memory cell block of the plurality of memory cells. The word line control circuit controls the word line to keep the cell transistor selected even after the memory cell block selection transistor is turned off.

Abstract: A semiconductor memory device for a flash EEPROM includes MOS transistors, each used as a fuse element for storing function control data and having a stacked gate structure in which a floating gate and a control gate are stacked on each other, and a sequence control circuit for pre-charging the drain of a MOS transistor as a fuse element upon reception of a predetermined control signal, reading out data from the MOS transistor after the pre-charge operation, and latching the readout data.

Abstract: In a semiconductor wafer (1), an internal circuit such as a ROM formed at a product region or a chip (2) can be tested via a test pad (5) formed on a scribe line (3). Here, since the test pad (5) is formed on the scribe line (3), after the semiconductor wafer has been once cut off and separated away from each other as chips along the scribe lines (3), respectively, since the test pads (5) are all broken off, ROM test will not be executed again. In other words, since the test conditions of the product test of the separated chip (2) cannot be decoded or deciphered by another person, it is possible to provide a semiconductor device of high secrecy, which can be preferably used as an IC card.

Abstract: A semiconductor memory device comprises a memory cell array comprising a plurality of nonvolatile memory cells each having a two-layer gate structure in which a floating gate and a control gate are stacked, and an auto-program/auto-erase control circuit for designating, on the basis of an erase command input, the plurality of memory cells in the memory cell array, in which data is to be erased, and automatically controlling a process, wherein the auto-program/auto-erase control circuit performs a program verify operation of a pre-program operation, repeats program and program verify operations until the program operation is completed, if the pre-program operation is necessary as a result of the program verify operation, performs erase verify operation at a time the pre-program operation is completed, and then repeats erase and erase verify operations until the erase operation is completed.

Abstract: A plurality of erase circuits are provided for the blocks BLK(0) to BLK(n), each for one block. Protect circuits are connected to the erase circuits, respectively. The protects circuits generate protect signals PROT0 to PROTn, respectively. Each protect signal indicates whether the protect circuit is set in protect mode or not. Each erase circuit receives the protect signal from the protect circuit connected to it. A unit provided in the erase circuit determines, from the protect signal, whether the protect circuit is set in the protect mode. The unit changes the voltage applied to the sources of the memory cells of the cell block connected to the erase circuit, in accordance with whether the protect circuit is set in the protect mode or not. When a voltage is applied to the sources of the memory cells, a data item of a logic value is read from each memory cell. When a different voltage is applied to the sources of the memory cells, a data item of the other logic value is read from each memory cell.