Abstract: A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract: Disclosed herein is a method of manufacturing a glass core capable of continuously manufacturing the glass core by an automated process. The method includes: providing a glass sheet; laminating an insulating sheet on the glass sheet; laminating a copper clad sheet on the insulating sheet to manufacture the glass core; laminating a buffering sheet on the copper clad sheet; pressing and temporarily hardening the buffering sheet; delaminating the temporarily hardened buffering sheet; thermally hardening the glass core by a heater after the delaminating of the temporarily hardened buffering sheet; and cutting the glass core at a predetermined size after the thermal hardening of the glass core.

Abstract: Disclosed herein is a multilayer printed circuit board. The multilayer printed circuit board according to the present invention includes: a stack via stacked in an upper portion of a core layer; staggered vias formed at both sides of the stack via and stacked on the core layer; and a solder resist layer stacked in a lower portion of the core layer and stacked on an insulating film except for open regions of the stack via and the staggered vias, such that the plurality of vias formed in the staggered via may increase rigidity to prevent warpage of the multilayer printed circuit board from being generated.

Abstract: There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board according to an exemplary embodiment of the present disclosure includes an insulating layer including a glass core and a tempering treatment layer formed on one surface of the glass core, such that a problem about warpage may be minimized and an effect capable of thinning the printed circuit board may be achieved.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract: In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

Abstract: Disclosed herein are a glass core substrate and a method for manufacturing the same. According to an embodiment of the present invention, there is provided the glass core substrate including: a glass core laminate including a glass layer and insulating layers which are stacked on upper and lower portions of the glass layer; a through hole formed by penetrating through the glass core laminate and provided with at least one crack which is formed at a penetrating inner wall by penetrating into the glass layer; and a conductive material filled in the through hole and the crack. Further, the method for manufacturing a glass core substrate is provided.

Abstract: Disclosed herein is a printed circuit board capable of implementing slimness by decreasing the number of entire layers through an asymmetrical build-up structure in which an electric device is embedded, the printed circuit board including: a core layer including a cavity formed therein so that an electric device is embedded and a circuit pattern and a pad formed on upper and lower surfaces thereof; a through via formed in the core layer so as to connect the upper and the lower pads of the core layer to each other; a plurality of insulating layers built-up on the core layer and including a plurality of vias so as to be electrically connected to the through via; and a solder resist layer applied onto a lower portion of the core layer so that a lower surface of the through via is partially exposed.

Abstract: Disclosed herein is a core made of a glass material so as to be capable of preventing generation of warpage in a printed circuit board due to a difference in a coefficient of thermal expansion at the time of manufacturing the printed circuit board. The core includes: an organic cloth; and a glass having the organic cloth formed therein. The core is manufactured in a form in which rigidity thereof is increased by impregnating the organic cloth having a negative coefficient of thermal expansion is impregnated in a liquid-phase glass, thereby making it possible to effectively prevent generation of warpage in the printed circuit board due to the difference in a coefficient of thermal expansion.

Abstract: In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

Abstract: A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line.

Abstract: A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.

Abstract: An image processing apparatus and an image processing method, the method including: providing one or more low dynamic range images having different exposure levels; classifying each of the one of more low dynamic range images as a saturation region, an under-saturation region, and a non-saturation region with respect to an intensity value; generating feature maps indicating a similarity between patterns of the non-saturation regions; generating final feature maps converting pixels included in the feature maps into moving pixels and non-moving pixels; defining moving regions and non-moving regions included in the one or more low dynamic range images; removing noise from the moving regions and the non-moving regions by using a first noise reduction filter for the moving regions and a second noise reduction filter for the non-moving regions; and generating a radiance map corresponding to the one or more low dynamic range images.

Abstract: Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract: A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract: Provided are a semiconductor package and a method of fabricating the same. In one embodiment, to fabricate a semiconductor package, a wafer having semiconductor chips fabricated therein is provided. A heat sink layer is formed over the wafer. The heat sink layer contacts top surfaces of the semiconductor chips. Thereafter, the plurality of semiconductor chips are singulated from the wafer.