Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.

Abstract: Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

Abstract: A method of fabricating a solar cell is disclosed. The solar cell fabricating method includes forming a first transparent conductive layer on a transparent substrate, texturing an upper surface of the first transparent conductive layer using an etchant solution configured to contain an acid with a molecular weight of about 58˜300, forming a photoelectric conversion layer on the first transparent conductive layer, forming a second transparent conductive layer on the photoelectric conversion layer, and forming a rear electrode on the second transparent conductive layer.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: A method of manufacturing a solar cell includes forming a transparent conductive layer on a substrate by depositing a transparent conductive oxide under room temperature, crystallizing the transparent conductive layer by irradiating a laser beam to the transparent conductive layer using a first laser; selectively etching the crystallized transparent conductive layer to form embossed and depressed patterns at a surface of the transparent conductive layer; forming transparent electrodes in unit cells by patterning the transparent conductive layer having the embossed and depressed patterns; forming a p-n junction semiconductor layer on the transparent electrodes and patterning the p-n junction semiconductor layer; and forming rear electrodes on the patterned p-n junction semiconductor layer by forming a metallic material layer and patterning the metallic material layer, the rear electrodes corresponding to the unit cells.

Abstract: The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes, and pixel electrodes connected to the second electrodes.

Abstract: A method of fabricating a solar cell is disclosed. The solar cell fabricating method includes forming a first transparent conductive layer on a transparent substrate, texturing an upper surface of the first transparent conductive layer using an etchant solution configured to contain an acid with a molecular weight of about 58˜300, forming a photoelectric conversion layer on the first transparent conductive layer, forming a second transparent conductive layer on the photoelectric conversion layer, and forming a rear electrode on the second transparent conductive layer.

Abstract: A method of manufacturing a thin film solar cell includes steps of preparing a substrate on which unit cells are defined, forming transparent conducive layers on the substrate and corresponding to the unit cells, respectively, the transparent conductive layers spaced apart from each other with a first separation line therebetween, forming light-absorbing layers on the transparent conductive layers and corresponding to the unit cells, respectively, the light-absorbing layers spaced apart from each other with a second separation line therebetween, forming a third separation line in each of the light-absorbing layers, the third separation line spaced apart from the second separation line, forming a reflection material layer by disposing a silk screen over the third separation line and applying a conductive paste, and forming reflection electrodes corresponding to the unit cells, respectively, by sintering the reflection material layer.

Abstract: A thin film solar cell includes a first substrate, a transparent conductive layer on an inner surface of the first substrate, the transparent conductive layer having an uneven top surface and including through-holes, a light-absorbing layer on the transparent conductive layer, a reflection electrode on the light-absorbing layer, a second substrate facing and attached with the first substrate, and a polymeric material layer on an inner surface of the second substrate.

Abstract: The present invention provides a thin film transistor array panel which includes a substrate, gate lines formed on the substrate, polycrystalline semiconductors formed on the gate lines, data lines formed on the polycrystalline semiconductors and including first electrodes, second electrodes formed on the polycrystalline semiconductors and facing the first electrodes, and pixel electrodes connected to the second electrodes.

Abstract: A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.

Abstract: A display device comprises: an insulating substrate; a first electrode formed over the insulating substrate and physically contacting the insulating substrate; an organic layer which is formed over the first electrode and includes an organic light emitting layer; and a second electrode which is formed over the organic layer.