Patents by Inventor Taek-Sang Song

Taek-Sang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10318187
    Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Il Park, Sang-Jin Byeon, Taek-Sang Song
  • Publication number: 20180046389
    Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 15, 2018
    Inventors: Il PARK, Sang-Jin BYEON, Taek-Sang SONG
  • Patent number: 9843325
    Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 12, 2017
    Assignee: SK Hynix Inc.
    Inventor: Taek-Sang Song
  • Patent number: 9793901
    Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: October 17, 2017
    Assignee: SK Hynix Inc.
    Inventors: Han-Kyu Chi, Kyung-Hoon Kim, Myeong-Jae Park, Taek-Sang Song, Tae-Wook Kang
  • Patent number: 9667261
    Abstract: An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 30, 2017
    Assignee: SK Hynix Inc.
    Inventors: Han-Kyu Chi, Taek-Sang Song
  • Publication number: 20170149435
    Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
    Type: Application
    Filed: December 14, 2016
    Publication date: May 25, 2017
    Inventor: Taek-Sang SONG
  • Publication number: 20170063384
    Abstract: An integrated circuit may include: a phase detector suitable for generating a delay control signal by comparing the phases of first and second clock signals to first and second target positions, a variable delay unit suitable for shifting the first and second clock signals to the first and second target positions, respectively, in response to the delay control signal, and a position controller suitable for varying the first and second target positions according to an operation mode.
    Type: Application
    Filed: January 13, 2016
    Publication date: March 2, 2017
    Inventors: Han-Kyu CHI, Kyung-Hoon KIM, Myeong-Jae PARK, Taek-Sang SONG, Tae-Wook KANG
  • Publication number: 20170041003
    Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
    Type: Application
    Filed: January 20, 2016
    Publication date: February 9, 2017
    Inventor: Taek-Sang SONG
  • Patent number: 9553585
    Abstract: A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: January 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Taek-Sang Song
  • Publication number: 20160352343
    Abstract: An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.
    Type: Application
    Filed: November 6, 2015
    Publication date: December 1, 2016
    Inventors: Han-Kyu CHI, Taek-Sang SONG
  • Publication number: 20160261437
    Abstract: An integrated circuit is provided that includes an equalizing unit suitable for equalizing input data that is successively inputted, a sampling unit suitable for sampling centers and edges of the input data that is equalized by the equalizing unit using two or more multi-phase clocks, and a gain adjustment unit suitable for adjusting a gain of the equalizing unit using the centers of the input data and the edges of the input data that are sampled by the sampling unit.
    Type: Application
    Filed: June 23, 2015
    Publication date: September 8, 2016
    Inventors: Han-Kyu CHI, Taek-Sang SONG, Dong-Wook JANG
  • Patent number: 9379881
    Abstract: A phase interpolator circuit that includes an interpolator suitable for generating synthesized clocks through synthesizing two multi-phase clocks; and an interpolation code generator suitable for generating an interpolation code for controlling the interpolator in response to a shift request. The interpolation code generator generates the interpolation code so that a (K+1)-th multi-phase clock is output as the synthesized clock when a phase of the synthesized clock is to be changed from a phase between K-th and (K+1)-th multi-phase clocks to a phase between (K+1)-th and (K+2)-th multi-phase clocks in response to a multi-shift-up request.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 28, 2016
    Assignee: SK Hynix Inc.
    Inventors: Han-Kyu Chi, Taek-Sang Song
  • Patent number: 9270275
    Abstract: A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 23, 2016
    Assignee: SK Hynix Inc.
    Inventor: Taek-Sang Song
  • Patent number: 9225346
    Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventors: Dae-Han Kwon, Yong-Ju Kim, Taek-Sang Song
  • Publication number: 20150207506
    Abstract: A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal.
    Type: Application
    Filed: June 10, 2014
    Publication date: July 23, 2015
    Inventor: Taek-Sang SONG
  • Patent number: 9071241
    Abstract: A semiconductor device includes a clock delay unit configured to delay a source clock by a given delay amount and generate a delayed source clock, a driving signal generation unit configured to decide logic levels of first and second driving signals based on a value of input data, to select one of the source clock and the delayed source clock based on current logic levels of the first and second driving signal's, which are detected based on the source clock, and to use a selected clock as a reference of an operation for determining next logic levels of the first and second driving signals, and an output pad driving unit configured to drive a data output pad with a first voltage in response to the first driving signal, and to drive the data output pad with a second voltage in response to the second driving signal.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 30, 2015
    Assignee: SK Hynix Inc.
    Inventors: Kwan-Su Shon, Taek-Sang Song
  • Patent number: 9059825
    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 16, 2015
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Han-Kyu Chi, Taek-Sang Song, Seok-Min Ye, Gi-Moon Hong, Woo-Rham Bae, Min-Seong Chu, Deog-Kyoon Jeong, Su-Hwan Kim
  • Publication number: 20150139289
    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.
    Type: Application
    Filed: September 26, 2014
    Publication date: May 21, 2015
    Inventors: Han-Kyu CHI, Taek-Sang SONG, Seok-Min YE, Gi-Moon HONG, Woo-Rham BAE, Min-Seong CHU, Deog-Kyoon JEONG, Su-Hwan KIM
  • Patent number: 9019746
    Abstract: A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyuck-Sang Yim, Taek Sang Song
  • Patent number: 9013222
    Abstract: An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventor: Taek-Sang Song