Abstract: A photonic biosensor including a biological probe disposed on a mid-infrared-transparent waveguide can be used to detect biological analytes in biological samples, using specific binding of the analyte to the probe in conjunction with absorption spectroscopy. In various embodiments, the biosensor is used for molecular diagnostics, e.g., to detect oligonucleotides or proteins associated with a coronavirus.

Abstract: Raman spectroscopy of chemical and biological samples can be accomplished with photonic sensors amenable to chip-scale integration. In various embodiments, such a photonic sensor includes first and second optical waveguides coupled via an optical ring resonator, the ring resonator configured to resonantly enhance, and selectively couple into the second optical waveguide, a Raman scattering signal generated, when the first waveguide and/or resonator are exposed to a sample, by interaction of an analyte in the sample with excitation light coupled into the first optical waveguide.

Abstract: A headset controller takes a first touch sensor, a second touch sensor, a first pressure sensor, and a second pressure sensor as a control medium for users. The headset controller can generate four different output instructions by the users touching or pressing the operating interface. The headset controller integrates various sensing methods to generate the needed output instructions.

Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: Disclosed herein are novel bifunctional compounds and their uses for the treatment and/or prophylaxis of cancers.

Abstract: An image sensor including a pixel matrix and an opaque layer is provided. The pixel matrix includes a plurality of unblocked pixels, a plurality of first pixels and a plurality of second pixels. The opaque layer covers upon a first region, which is a part of each first pixel, and upon a second region, which is a part of each second pixel, but does not cover upon the unblocked pixels, wherein the first region and the second region are symmetrically arranged in a first direction, and uncovered regions of the first pixels and the second pixels are arranged to be larger at a pixel edge than at a pixel center.

Abstract: A polymer fiber tubular structure includes a first pipe element, a second pipe element, and a coil winding structure, wherein the first pipe element includes an inner surface and an outer surface and is composed of silicon-containing polycarbonate type polyurethane elastomer, the second pipe element includes an inner surface and an outer surface and is composed of polycarbonate type polyurethane elastomer. The second pipe element is wrapped on the outer surface of the first pipe element such that the first pipe element and the second pipe element are concentric structures. The coil winding structure is provided for embedding into the outer surface of the first pipe element or into the outer surface of the second pipe element, thereby, the kinking of the polymer fiber tubular structure is to be reduced during use, and the thrombosis can be further avoided when the polymer fiber tubular is used for the human being.

Abstract: In one example, an electronic device may include a battery, a measuring unit to record a plurality of temperature readings associated with an operation of the battery at particular time intervals, and a control unit coupled to the measuring unit. The control unit may retrieve a set of temperature readings corresponding to a period from the plurality of temperature readings, analyze the set of temperature readings corresponding to the period to determine whether a temperature of the battery exceeds a threshold, and reduce a charging voltage of the battery in response to a determination that the temperature of the battery exceeds the threshold.

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: An imaging device including a condenser lens and an image sensor is provided. The image sensor is configured to sense light penetrating the condenser lens and includes a pixel matrix, an opaque layer, a plurality of microlenses and an infrared filter layer. The pixel matrix includes a plurality of infrared pixels, a plurality of first pixels and a plurality of second pixels. The opaque layer covers upon a first region of the first pixels and a second region of the second pixels, wherein the first region and the second region are mirror-symmetrically arranged in a first direction. The plurality of microlenses is arranged upon the pixel matrix. The infrared filter layer covers upon the infrared pixels.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).