Abstract: A polymer fiber tubular structure includes a first pipe element, a second pipe element, and a coil winding structure, wherein the first pipe element includes an inner surface and an outer surface and is composed of silicon-containing polycarbonate type polyurethane elastomer, the second pipe element includes an inner surface and an outer surface and is composed of polycarbonate type polyurethane elastomer. The second pipe element is wrapped on the outer surface of the first pipe element such that the first pipe element and the second pipe element are concentric structures. The coil winding structure is provided for embedding into the outer surface of the first pipe element or into the outer surface of the second pipe element, thereby, the kinking of the polymer fiber tubular structure is to be reduced during use, and the thrombosis can be further avoided when the polymer fiber tubular is used for the human being.

Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: An imaging device including a condenser lens and an image sensor is provided. The image sensor is configured to sense light penetrating the condenser lens and includes a pixel matrix, an opaque layer, a plurality of microlenses and an infrared filter layer. The pixel matrix includes a plurality of infrared pixels, a plurality of first pixels and a plurality of second pixels. The opaque layer covers upon a first region of the first pixels and a second region of the second pixels, wherein the first region and the second region are mirror-symmetrically arranged in a first direction. The plurality of microlenses is arranged upon the pixel matrix. The infrared filter layer covers upon the infrared pixels.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A physiological detection device including a light source, an image sensor and a processor is provided. The light source illuminates a skin surface using a burst mode. The image sensor receives ejected light from skin tissues under the skin surface at a sampling frequency to successively generate image frames. The processor controls the light source and the image sensor, and calculates a physiological characteristic according to the image frames captured when the light source is illuminating light. The physiological detection device reduces the total power consumption by adopting the burst mode.

Abstract: An optical fingerprint sensor is provided. The optical fingerprint sensor includes a substrate, a light-shielding layer and an optical material layer. The light-shielding layer is disposed on the substrate. The optical material layer is in contact with the light-shielding layer. The optical material layer includes a non-filtering portion and a filtering portion.

Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.

Abstract: Disclosed herein are novel bifunctional compounds and their uses for the treatment and/or prophylaxis of cancers. The bifunctional compound disclosed herein has the structure of formula (I).

Abstract: An optical sensor includes an optical layer disposed on a substrate, and a light shielding layer disposed on the optical layer, wherein the light shielding layer includes a first opening that partially exposes the optical layer. The optical sensor also includes a polymer material layer that fills the first opening, wherein a top surface of the polymer material layer is higher than a top surface of the light shielding layer. The optical sensor further includes an adhesive layer disposed on the light shielding layer and the polymer material layer, and a surface component disposed on the adhesive layer.

Abstract: A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Abstract: A system and a method for improving continuous load transition of a DC-DC converter are provided. The system includes a conduction detector circuit, a counter circuit, a depth control circuit and a slope generator. The conduction detector circuit detects a phase signal of the DC-DC converter to generate a pulse signal. The counter circuit counts the number of pulse waves of the pulse signal to output a counting signal. The depth control circuit generates a pulled-down depth signal. The slope generator generates a slope signal according to the pulled-down depth signal. The pulled-down depth signal is pulled down by a first depth each time the switch circuit is conducted, but when the number of times that the switching circuit is conducted reaches a conduction number threshold, the pulled-down depth signal is pulled down by a second depth that is larger than the first depth.

Abstract: A waveguide structure including a mid-infrared-transparent waveguide on a mid-infrared-transparent undercladding may serve as a photonic chemical sensor for measuring characteristic absorptions of analytes brought in physical contact with the waveguide. In some embodiments, a sensor including an amorphous-silicon waveguide on a barium-titanate undercladding can operate at wavelengths ranging from 2.5 ?m to about 7 ?m; this sensor may be manufactured by epitaxial growth of the undercladding on a substrate, followed by CMOS-compatible creation of the waveguide. Additional embodiments are disclosed.

Abstract: A multi-phase DC-DC power converter includes an error amplifier, a comparator, a phase selection circuit, a plurality of phase circuits and a width detecting circuit. The plurality of phase circuits are each associated with a phase of the multi-phase DC-DC power converter, each including a turn-on clock generation circuit, a first switching transistor, a second switching transistor, an output inductor, and a control logic. In a load transition state, when the width detecting circuit detects that a comparison output signal exceeds a predetermined width, the phase selection circuit adjusts one of the plurality of phase signals based on a force trigger signal, and outputs, corresponding to a force trigger signal, one of the plurality of on-signals.