Patents by Inventor Takahiro Maruyama

Takahiro Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150206787
    Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.
    Type: Application
    Filed: January 9, 2015
    Publication date: July 23, 2015
    Inventors: Tatsunori Murata, Takahiro Maruyama
  • Patent number: 8951860
    Abstract: The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Ishii, Hiraku Chakihara, Takahiro Maruyama, Akihiro Nakae
  • Publication number: 20140363363
    Abstract: A rectangular substrate 12 composed of c-plane sapphire is prepared. Nickel serving as a catalytic metal is deposited on the entirety of an upper surface of the substrate 12 to form a catalytic metal film 14 (see (a)). The catalytic metal film 14 is patterned by a lithography method into a catalytic metal film 16 having a predetermined shape (see (b)). The temperature of the catalytic metal film 16 is raised to 1000° C. and maintained at 1000° C. for 20 minutes. The temperature of the catalytic metal film 16 is lowered from 1000° C. to 800° C. at a rate of 5° C./min. The temperature of the catalytic metal film 16 is maintained at 800° C. for 15 hours. Thereby, a catalytic metal layer 17 having large grains is provided (see (c)).
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventors: Shigeya NARITSUKA, Takahiro MARUYAMA
  • Publication number: 20140263441
    Abstract: Provided is a portion container compression system capable of preventing a portion container from being misaligned, and being used without contaminating surrounding items even when misalignment occurs. A content can be pushed out by squeezing the portion container installed in a receiving portion of a system main body, and formed on the front region of the portion container is an easily unsealable portion. The portion container is formed into an asymmetric shape in the front-back direction, and the receiving portion has a misalignment-prevention portion allowing the front region of the portion container to be aligned to the receiving portion, but preventing the back region thereof from being aligned to the receiving portion. The misalignment-prevention portion prevents the ejection from a misaligned portion container. Since there cannot be achieved the effects as those when the portion container is correctly installed, a user may notice the misalignment of the portion container.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: Thermos K.K.
    Inventors: Takahiro Maruyama, Shin Matsuyama, Hiroki Yokoyama
  • Publication number: 20140261003
    Abstract: Provided is a portion container system having improved operability and user-friendliness. The system includes a receiving portion, for stowing a container on a system main body, and a rotatable handle. The container includes a peeling induction portion. The container, stowed in the receiving portion, is allowed to be compressed by swinging a handle. The container can be squeezed with the handle using the leverage, thus improving a convenience and allowing the system to be formed compact compared to a rotary apparatus. Since the container is obliquely placed in the receiving portion, the content ejected hardly splashes. Since the receiving portion is located below the rotation center shaft of the handle, the container is pressed with the handle having the rotation center shaft located above the receiving portion, thereby causing the container to be pressed with the force pushing down the handle, thus allowing for easy application of force.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: Thermos K.K.
    Inventors: Takahiro Maruyama, Shin Matsuyama
  • Publication number: 20140211163
    Abstract: The slit lamp microscope is capable of easily adjusting a slit-light and a backlight. The slit lamp microscope comprises: a slit lamp for emitting a slit-light; a mirror unit having a reflecting mirror or a prism, which reflects the slit-light emitted from the slit lamp toward an eye of an examinee; a microscope unit for observing the eye of the examinee; and a backlight source for emitting a backlight, which illuminates a circumference of the slit-light, toward the eye of the examinee. The backlight source is provided to the mirror unit.
    Type: Application
    Filed: September 30, 2013
    Publication date: July 31, 2014
    Applicant: Takagi Seiko Co., Ltd.
    Inventors: Takahiro MARUYAMA, Takeshi NARA, Shigeo KANAZAWA
  • Patent number: 8754471
    Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Kozo Ishikawa, Masashi Kitazawa, Kiyoshi Hayashi, Takahiro Maruyama, Masaaki Shinohara, Kenji Kawai
  • Patent number: 8697446
    Abstract: The present invention relates to a cell fusion chamber in which two types of cells having different diameters are fused, the cell fusion chamber including: a cell fusion region in which cell fusion is carried out; a pair of electrodes formed by a conductor and disposed opposite to each other in the cell fusion region; and a partition wall having at least one fine pore; near the fine pore, a cell fusion device including a cell fusion container containing a cell fusion region; a pair of electrodes; a spacer; and an insulator disposed between the spacer and one of the electrodes and having at least one fine pore; and an electronic power supply which applies an alternating voltage and a voltage pulsed direct current to the electrodes, and a cell fusion method using the same.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 15, 2014
    Assignee: Tosoh Corporation
    Inventors: Toru Futami, Takahiro Maruyama, Atsushi Morimoto
  • Patent number: 8552343
    Abstract: Disclosed is a brazing structure that includes a ceramic member, a metal layer, a tubular metal fitting and first and second brazing members. The ceramic member includes a small diameter portion and a large diameter portion. The metal layer is located on an outer surface of the large diameter portion. At least an edge of the ceramic member is inserted in the fitting. The first brazing member connects the inner surface of the fitting to the metal layer. The second brazing member does not contact with the metal layer, and fills between at least a part of the small diameter portion and the inner surface, which faces to the part of the small diameter portion, of the fitting. The small diameter portion is located closer to the edge than the metal layer and is inside the fitting.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Kyocera Corporation
    Inventor: Takahiro Maruyama
  • Patent number: 8536005
    Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Maruyama, Masao Inoue
  • Publication number: 20130084684
    Abstract: The present invention improves the production yield of a semiconductor device having nonvolatile memory cells of a split gate structure. The level difference of a lower layer resist film with which an end of a memory mat is covered is gentled, the uniformity of the thickness of a resist intermediate layer formed over the lower layer resist film is improved, and local thickness reduction or disappearance is prevented by, after forming a silicon oxide film and a silicon nitride film over each of selective gate electrodes formed in a memory cell region of a semiconductor substrate, removing the silicon oxide film and the silicon nitride film over the selective gate electrode located on the outermost side (a dummy cell region) of the memory mat in the gate length direction.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 4, 2013
    Inventors: Yasushi ISHII, Hiraku CHAKIHARA, Takahiro MARUYAMA, Akihiro NAKAE
  • Publication number: 20130011899
    Abstract: The present invention relates to a cell fusion chamber in which two types of cells having different diameters are fused, the cell fusion chamber including: a cell fusion region in which cell fusion is carried out; a pair of electrodes formed by a conductor and disposed opposite to each other in the cell fusion region; and a partition wall having at least one fine pore; near the fine pore, a cell fusion device including a cell fusion container containing a cell fusion region; a pair of electrodes; a spacer; and an insulator disposed between the spacer and one of the electrodes and having at least one fine pore; and an electronic power supply which applies an alternating voltage and a voltage pulsed direct current to the electrodes, and a cell fusion method using the same.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: TOSOH CORPORATION
    Inventors: Toru FUTAMI, Takahiro Maruyama, Atsushi Morimoto
  • Patent number: 8334054
    Abstract: A heat conductive cured product which can be handled even in a single layer or thin film form, can be readily attached to a heat-generating component or heat-dissipating member, and exhibits an appropriate tack and heat conductivity in a thin film form is provided as well as a method for preparing the same. A heat conductive cured product is prepared by applying a heat conductive composition as a thin film to a substrate which has been treated to have a silicone pressure-sensitive adhesive releasable surface, and curing the composition, the composition comprising as essential components, (a) an organopolysiloxane having alkenyl radicals, (b) a heat conductive filler, the filler containing at least 30 vol % of aluminum powder based on its total volume, (c) an organohydrogenpolysiloxane, (d) a platinum group metal catalyst, (e) a reaction regulator, and (f) a silicone resin.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: December 18, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Akihiro Endo, Masaya Asaine, Takahiro Maruyama
  • Patent number: 8324535
    Abstract: A ceramic heater comprising a rod-like ceramic member in which a metallized layer is formed on at least a part of an outer surface of the ceramic member, and a tubular metal fitting in which at least a part of the ceramic member is inserted, the inner surface of the tubular metal fitting and the metallized layer being brazed through a brazing member. The ceramic member has a small diameter portion in a region which is located closer to a first end of the ceramic member than the metallized layer and which is inside the tubular metal fitting. A part of the space between the small diameter portion and the inner surface of the tubular metal fitting is filled with the brazing member, the inner surface facing to the part of the small diameter. Consequently, even under severe conditions, such as a high temperature and/or a high pressure, a highly durable brazing structure, such as the ceramic heater, including a brazed portion which has high welding reliability can be obtained.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: December 4, 2012
    Assignee: Kyocera Corporation
    Inventor: Takahiro Maruyama
  • Patent number: 8277770
    Abstract: Carbon atoms are fed to a catalytic metal particle 10 having a atomic arrangement of triangular lattices in a round (or partly round) of a side wall, and a graphen sheet 18 having a six-membered structure reflecting the atomic arrangement of the triangular lattices is consecutively formed by the metal catalyst, whereby a tubular structure of the carbon atoms is formed. Thus, the chirality of the tubular structure can be controlled by the growth direction of the graphen sheet with respect to the direction of the triangular lattices, and the diameter of the tubular structure can be controlled by the size of the catalytic metal particle.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: October 2, 2012
    Assignees: Fujitsu Limited, Meijo University Educational Foundation
    Inventors: Yuji Awano, Shigeya Naritsuka, Akio Kawabata, Takahiro Maruyama
  • Publication number: 20120049288
    Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.
    Type: Application
    Filed: August 4, 2011
    Publication date: March 1, 2012
    Inventors: Takahiro MARUYAMA, Masao Inoue
  • Publication number: 20110215423
    Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 8, 2011
    Inventors: Toshiaki IWAMATSU, Kozo ISHIKAWA, Masashi KITAZAWA, Kiyoshi HAYASHI, Takahiro MARUYAMA, Masaaki SHINOHARA, Kenji KAWAI
  • Patent number: 7989283
    Abstract: A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Yamanari, Ryoichi Yoshifuku, Masaaki Shinohara, Takahiro Maruyama, Kenji Kawai, Yusaku Hirota
  • Publication number: 20110081753
    Abstract: A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 7, 2011
    Inventors: Shinichi YAMANARI, Ryoichi Yoshifuku, Masaaki Shinohara, Takahiro Maruyama, Kenji Kawai, Yusaku Hirota
  • Publication number: 20110033910
    Abstract: The cell selection apparatus includes: a cell selection vessel which has a pair of electrodes and a sheet-like insulating material having a plurality of micropores, with a recognition molecule bindable to the specific substance being disposed on a bottom face of the micropore; and a power supply, wherein the power supply includes a cell-immobilization power supply and a cell-taking power supply. The cell selection method uses the cell selection apparatus, including; introducing cells into a cell selection area; immobilizing these cells in the micropores; effecting a binding reaction between the specific substance and the recognition molecule; thereafter, taking out a cell of which the specific substance is not or is weakly bound to the recognition molecule, from the micropore; otherwise alternatively, leaving a cell of which the specific substance on the surface of the cell is strongly bound to the recognition molecule, behind in the micropore.
    Type: Application
    Filed: April 15, 2009
    Publication date: February 10, 2011
    Applicant: TOSOH CORPORATION
    Inventors: Maho Yamanaka, Takahiro Maruyama, Toru Futami