Patents by Inventor Takahiro Naito

Takahiro Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8653655
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Publication number: 20130320571
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Application
    Filed: August 6, 2013
    Publication date: December 5, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8524534
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8427078
    Abstract: A light-emitting element driving device includes: a plurality of light emitters; a power supply; a plurality of current control transistors; a plurality of constant-current circuits; a voltage selecting circuit; a control circuit; and a voltage controller.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: April 23, 2013
    Assignee: Sony Corporation
    Inventors: Takahiro Naito, Yasushi Katayama, Tatsuki Nishino
  • Patent number: 8324736
    Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20120264240
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Application
    Filed: June 26, 2012
    Publication date: October 18, 2012
    Inventors: Yoshiyuki KADO, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kirkuchi
  • Patent number: 8278147
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Publication number: 20120136553
    Abstract: A control apparatus controls an automatic stop of an engine mounted on a vehicle so as to automatically stop the engine if a predetermined stop condition is satisfied, the stop condition including a condition that a running speed of the vehicle is a prescribed speed or less. The control apparatus includes a prediction unit and a prohibition unit. The prediction unit predicts whether or not the next automatic stop time of the engine is less than a prescribed time capable of obtaining a fuel saving benefit based on a history of a vehicle stop time or an automatic stop time of the engine. The prohibition unit prohibits the next automatic stop of the engine if the prediction unit predicts that the next automatic stop time of the engine is less than the prescribed time.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 31, 2012
    Applicant: DENSO CORPORATION
    Inventors: Takayuki TAKEUCHI, Kenji KAWAHARA, Hiroshi MORIMOTO, Takahiro NAITO, Takanori SASAKI
  • Patent number: 8178977
    Abstract: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: May 15, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20120108055
    Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro YOSHIMURA, Naotaka TANAKA, Michihiro KAWASHITA, Takahiro NAITO, Takashi AKAZAWA
  • Publication number: 20120091583
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 19, 2012
    Inventors: Michihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: 8132974
    Abstract: An image generating apparatus includes a print portion printing a paper, a platen roller arranged so as to be opposed to the print portion, a heat radiating member mounted on the print portion, radiating heat generated in the print portion, integrally provided with a plate-like support shaft as an axis of rotation and rotatable in a direction for coming into pressure contact with or separating from the platen roller, a regulating member regulating movement of the print portion in a printing direction of the paper, a chassis having a hole-shaped bearing receiving the plate-like support shaft, and a side plate mounted on the chassis.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: March 13, 2012
    Assignee: Funai Electric Co., Ltd.
    Inventors: Kunio Sawai, Takahiro Naito
  • Patent number: 8110900
    Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
  • Patent number: 8106518
    Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Publication number: 20110285313
    Abstract: A light-emitting element driving device includes: a plurality of light emitters; a power supply; a plurality of current control transistors; a plurality of constant-current circuits; a voltage selecting circuit; a control circuit; and a voltage controller.
    Type: Application
    Filed: March 3, 2011
    Publication date: November 24, 2011
    Applicant: Sony Corporation
    Inventors: Takahiro Naito, Yasushi Katayama, Tatsuki Nishino
  • Publication number: 20110285685
    Abstract: Disclosed herein is a light-emitting element driver including: a light-emitting section; a power supply section; a switching section; a constant current circuit or resistor; and a control circuit.
    Type: Application
    Filed: March 7, 2011
    Publication date: November 24, 2011
    Applicant: Sony Corporation
    Inventors: Takahiro Naito, Tatsuki Nishino, Takuro Akiyama, Yasushi Katayama
  • Publication number: 20110233773
    Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
  • Patent number: D653647
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: February 7, 2012
    Assignee: Sony Corporation
    Inventor: Takahiro Naito
  • Patent number: RE43443
    Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 5, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Yujiro Kajihara, Kazunari Suzuki, Kunihiro Tsubosaki, Hiromichi Suzuki, Yoshinori Miyaki, Takahiro Naito, Sueo Kawai
  • Patent number: D699210
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: February 11, 2014
    Assignee: Sony Corporation
    Inventor: Takahiro Naito