Patents by Inventor Takahiro Naito
Takahiro Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110171780Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 7973415Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: GrantFiled: June 5, 2008Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 7922406Abstract: In this image generating apparatus, a driving gear portion is so formed that the diameter of the outer peripheral surface of a first toothless portion is smaller than the tip diameter of a first toothed portion, and so arranged that the first toothless portion thereof slides on a second toothed portion of a driven gear portion of a print head rotating member in the vicinity of a position where a print head presses a platen roller with a pressing portion.Type: GrantFiled: February 7, 2008Date of Patent: April 12, 2011Assignee: Funai Electric Co., Ltd.Inventors: Kunio Sawai, Takahiro Naito
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Patent number: 7859095Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: April 7, 2009Date of Patent: December 28, 2010Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 7847413Abstract: A semiconductor device having a microcomputer chip and a plurality of high-speed memory chips and capable of making wiring lines of the memory chips equal in length is disclosed. The semiconductor device comprises a first wiring substrate, a microcomputer chip mounted over the first wiring substrate, a second wiring substrate disposed over the microcomputer chip, a plurality of first solder bumps for connecting the first and second wiring substrates with each other, and a plurality of second solder bumps as external terminals formed over a back surface of the wiring substrate. A first memory chip and a second memory chip, as high-speed memory chips, are stacked within the second wiring substrate, wiring of the first memory chip and that of the second memory chip are made equal in length within the second wiring substrate, and a completed package structure having the second wiring substrate is mounted over a completed package structure having the first wiring substrate.Type: GrantFiled: May 16, 2007Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Toshihiko Akiba, Takahiro Naito
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Patent number: 7810806Abstract: This paper feed mechanism includes a paper feed cassette integrally having a paper contact portion on a position deviating from the center of a rear-side inner wall surface in the cross direction by a prescribed distance in the cross direction and an apparatus body mountable with the paper feed cassette, and the apparatus body includes a driving portion rotating a paper feed roller in a paper feed direction and a paper discharge direction and a control portion bringing the rear end of the paper into contact with the paper contact portion for generating torque for the paper and thereafter transporting the paper to the apparatus body in paper feeding.Type: GrantFiled: June 17, 2008Date of Patent: October 12, 2010Assignee: Funai Electric Co., Ltd.Inventors: Daisuke Takasaka, Takahiro Naito
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Patent number: 7759161Abstract: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.Type: GrantFiled: January 27, 2006Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
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Patent number: 7753604Abstract: An ink sheet cartridge provided with a bobbin case easy to assemble and disassemble, formed with no protrusion on the outer surface thereof and capable of inhibiting the number of components from increase is obtained. This ink sheet cartridge is provided with a pawl and a receiving portion on upper and lower components respectively. The pawl is provided with a projecting engaging portion, and the receiving portion is provided with a groove engaging with the engaging portion. The groove has a guide for guiding the engaging portion and a stop portion fixing the engaging portion.Type: GrantFiled: March 17, 2006Date of Patent: July 13, 2010Assignee: Funai Electric Co., Ltd.Inventor: Takahiro Naito
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Publication number: 20100155940Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: ApplicationFiled: December 17, 2009Publication date: June 24, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka Tanaka, Takahiro NAITO, Takashi AKAZAWA
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Publication number: 20100015760Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: September 23, 2009Publication date: January 21, 2010Inventors: Yoshiyuki KADO, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20090309218Abstract: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.Type: ApplicationFiled: June 12, 2009Publication date: December 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka TANAKA, Takahiro NAITO, Takashi AKAZAWA
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Patent number: 7593027Abstract: This image generating apparatus includes a chassis and a side plate, a cartridge stop member provided on a first side surface of the chassis integrally has a first shaft stop portion coming into contact with a first end surface of a shaft of a print head pressing member, and a side plate provided on a second side surface of the chassis integrally has a second shaft stop portion coming into contact with a second end surface of the shaft of the print head pressing member.Type: GrantFiled: February 7, 2008Date of Patent: September 22, 2009Assignee: Funai Electric Co., Ltd.Inventors: Kunio Sawai, Takahiro Naito
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Patent number: 7584050Abstract: A driver's action at a target intersection in a guided route is predicted based on driving data. When the driver is attempting to go straight ahead at a target intersection where the driver should make a turn, or when the driver is attempting to make a turn at a target intersection where the driver should go straight ahead, the predicted driver's action is determined to disagree with the guided route. In this case, an execution of an audio guidance is performed but re-execution is awaited for a predetermined period. Further, when the driver is attempting to go straight ahead at a target intersection where the driver should make a turn, an audio guidance is executed after a distance to the target intersection is determined to be smaller than a required distance computed from a vehicle speed.Type: GrantFiled: September 23, 2005Date of Patent: September 1, 2009Assignee: DENSO CORPORATIONInventors: Takahiro Naito, Takafumi Ito
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Publication number: 20090189268Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: April 7, 2009Publication date: July 30, 2009Inventors: Yoshiyuki KADO, Takahiro Naito, Hikaru Ikegami, Takafumi Kikuchi, Toshihiko Sato
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Publication number: 20090189256Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Inventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
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Patent number: 7531441Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: April 7, 2006Date of Patent: May 12, 2009Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Publication number: 20090014843Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: ApplicationFiled: June 5, 2008Publication date: January 15, 2009Inventors: Michihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20080315500Abstract: This paper feed mechanism includes a paper feed cassette integrally having a paper contact portion on a position deviating from the center of a rear-side inner wall surface in the cross direction by a prescribed distance in the cross direction and an apparatus body mountable with the paper feed cassette, and the apparatus body includes a driving portion rotating a paper feed roller in a paper feed direction and a paper discharge direction and a control portion bringing the rear end of the paper into contact with the paper contact portion for generating torque for the paper and thereafter transporting the paper to the apparatus body in paper feeding.Type: ApplicationFiled: June 17, 2008Publication date: December 25, 2008Applicant: Funai Electric Co., Ltd.Inventors: Daisuke TAKASAKA, Takahiro NAITO
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Publication number: 20080248611Abstract: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature.Type: ApplicationFiled: February 27, 2008Publication date: October 9, 2008Inventors: Kenji HANADA, Norihisa Toma, Masaki Nakanishi, Takahiro Naito, Naotaka Tanaka
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Patent number: D602466Type: GrantFiled: December 12, 2008Date of Patent: October 20, 2009Assignee: Sony CorporationInventors: Takuro Hibino, Takahiro Naito