Patents by Inventor Takahiro Naito
Takahiro Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20050263869Abstract: To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip.Type: ApplicationFiled: May 25, 2005Publication date: December 1, 2005Applicants: Renesas Technology Corp., Hitachi, Ltd.Inventors: Naotaka Tanaka, Norio Nakazato, Takahiro Naito
-
Publication number: 20050029673Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.Type: ApplicationFiled: September 14, 2004Publication date: February 10, 2005Applicant: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Patent number: 6836021Abstract: A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.Type: GrantFiled: November 3, 2003Date of Patent: December 28, 2004Assignee: Renesas Technology Corp.Inventors: Toshikazu Ishikawa, Takahiro Naito, Hiroshi Kuroda, Yoshinari Hayashi
-
Patent number: 6800945Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.Type: GrantFiled: April 5, 2002Date of Patent: October 5, 2004Assignee: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Publication number: 20040178502Abstract: A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.Type: ApplicationFiled: November 3, 2003Publication date: September 16, 2004Applicant: Renesas Technology Corp.Inventors: Toshikazu Ishikawa, Takahiro Naito, Hiroshi Kuroda, Yoshinari Hayashi
-
Publication number: 20040164385Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: ApplicationFiled: December 5, 2003Publication date: August 26, 2004Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hiraku Ikegami, Takafumi Kikuchi
-
Publication number: 20040140544Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: ApplicationFiled: December 18, 2003Publication date: July 22, 2004Applicant: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Publication number: 20040130036Abstract: A compact multi-chip module having a high performance is provided. A plurality of first semiconductor chips for exchanging signals are surface-mounted on a surface of a mounting board. A second semiconductor chip with most of bonding pads thereof arranged along one side thereof is mounted back-to-back with at least one of the first semiconductor chips on the mounting board. The bonding pads of the second semiconductor chip and corresponding electrodes formed on the mounting board are connected by wire bonding. The first and second semiconductor chips and bonding wires on the mounting board are encapsulated with a sealing material.Type: ApplicationFiled: November 18, 2003Publication date: July 8, 2004Applicants: Renesas Technology Corp., Shinko Electric Industries Co., Ltd.Inventors: Masanori Owaki, Toshikazu Ishikawa, Takahiro Naito, Makoto Suzuki, Takafumi Kikuchi, Takashi Ozawa
-
Publication number: 20040109422Abstract: A radio base station apparatus capable of improving accuracy of synchronization detection and making stable determination of reception synchronization without erroneous synchronization determination is provided.Type: ApplicationFiled: November 26, 2003Publication date: June 10, 2004Applicant: NEC CORPORATIONInventor: Takahiro Naito
-
Publication number: 20040101071Abstract: A decoding apparatus includes a radio section, TFCI decoding characteristic feedback section, and dedicated physical data channel correcting section. The radio section receives data on a dedicated physical control channel and data on a dedicated physical data channel, which are coded into a complex code of a single system which is to be transmitted as an uplink signal from a mobile unit to a base station in a 3rd generation cell phone system. The TFCI decoding characteristic feedback section determines the TFCI decoding characteristics of a coded TFCI code on the dedicated physical control channel. The dedicated physical data channel correcting section performs data correction for the dedicated physical data channel on the basis of a determination result on the TFCI decoding characteristics. A decoding method and radio base station apparatus are also disclosed.Type: ApplicationFiled: November 19, 2003Publication date: May 27, 2004Inventor: Takahiro Naito
-
Patent number: 6727583Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: GrantFiled: March 7, 2002Date of Patent: April 27, 2004Assignee: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Patent number: 6646350Abstract: In order to realize a semiconductor device and a manufacturing method thereof which can keep with a high reliability an electric connection between each of bump pads formed on LSI chips and each of electrode pads formed on an interconnection substrate, within an guaranteed temperature range, a thermal expansion coefficient of an adhesive (3) is in the range of 20 to 60 ppm, and an elastic modulus of a build-up portion (6) is in the range of 5 to 10 GPa. Further, the build-up portion (6) is constituted by a multi-layer build-up substrate in which buid-up portion a peak value (a glass transition temperature) of a loss coefficient exists within a range of 100° C. to 250° C. and does not exist within a range of 0° C. to 100° C.Type: GrantFiled: August 3, 2001Date of Patent: November 11, 2003Assignee: Hitachi, Ltd.Inventors: Naotaka Tanaka, Hideo Miura, Yoshiyuki Kado, Ikuo Yoshida, Takahiro Naito
-
Publication number: 20030102570Abstract: An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.Type: ApplicationFiled: October 25, 2002Publication date: June 5, 2003Applicant: Hitachi, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Norio Kishikawa, Yoshiyuki Kado, Kazuyuki Taguchi, Takahiro Naito, Toshihiko Sato
-
Patent number: 6492737Abstract: An electronic device comprising: a semiconductor chip having plural electrode pads on one main surface thereof; a wiring board having plural connection parts; and plural salient electrodes disposed respectively between the electrode pads of the semiconductor chip and the connection parts of the wiring board to provide electrical connections between the two, the salient electrodes being arranged in an array not providing balance of the semiconductor chip with respect to one main surface of the wiring board, the plural connection parts of the wiring board being arranged at a deeper position than one main surface of the wiring board in a depth direction from the one main surface.Type: GrantFiled: August 6, 2001Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Norio Kishikawa, Yoshiyuki Kado, Kazuyuki Taguchi, Takahiro Naito, Toshihiko Sato
-
Publication number: 20020145204Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.Type: ApplicationFiled: April 5, 2002Publication date: October 10, 2002Applicant: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Publication number: 20020125565Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: ApplicationFiled: March 7, 2002Publication date: September 12, 2002Applicant: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
-
Patent number: D503392Type: GrantFiled: January 15, 2004Date of Patent: March 29, 2005Assignee: Sony CorporationInventors: Takahiro Naito, Koichi Maruta
-
Patent number: D503393Type: GrantFiled: January 16, 2004Date of Patent: March 29, 2005Assignee: Sony CorporationInventors: Takahiro Naito, Koichi Maruta
-
Patent number: D503394Type: GrantFiled: May 21, 2004Date of Patent: March 29, 2005Assignee: Sony CorporationInventor: Takahiro Naito
-
Patent number: D508936Type: GrantFiled: May 25, 2004Date of Patent: August 30, 2005Assignee: Sony CorporationInventor: Takahiro Naito