Patents by Inventor Takashi Imoto

Takashi Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050253247
    Abstract: There is disclosed a semiconductor device comprising at least one semiconductor element, one chip mounting base being provided at least one first interconnection on one major surface thereof and at least one second interconnection on the other major surface thereof, and the semiconductor element being electrically connected to at least the one first interconnection and mounted on the one major surface, a sealing member being provided on the one major surface of the chip mounting base and covering the semiconductor element and the first interconnection, at least one third interconnection being provided on a surface of the sealing member, and at least one fourth interconnection being provided in the sealing member and the chip mounting base, and electrically connected to the first interconnection, the second interconnection, and the third interconnection.
    Type: Application
    Filed: July 7, 2004
    Publication date: November 17, 2005
    Inventors: Takashi Imoto, Chiaki Takubo
  • Publication number: 20050254084
    Abstract: As an example of an embodiment, there is disclosed a notifying method of notifying the user of information regarding an apparatus in an information processing apparatus which can simultaneously provide an environment, as a user session, which can activate a user's desired program to each of a plurality of users. This method has: an obtaining step of obtaining the information regarding the apparatus; a specifying step of specifying the user session which uses a display unit of the information processing apparatus; and an activating step of activating a display program for displaying the information obtained in the obtaining step by the user session specified in the specifying step.
    Type: Application
    Filed: August 25, 2003
    Publication date: November 17, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventor: Takashi Imoto
  • Publication number: 20050212145
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed from the surface of the semiconductor substrate so that the semiconductor substrate is exposed at the portion, a mounting substrate on which the semiconductor element is mounted, and a resin layer which seals at least a surface side of the semiconductor element with resin.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 29, 2005
    Inventors: Takashi Imoto, Chiaki Takubo, Ryuji Hosokawa, Yoshihisa Imori, Takao Sato, Tetsuya Kurosawa, Mika Kiritani
  • Publication number: 20050063651
    Abstract: An optical semiconductor module comprises an optical transmission channel including a waveguide transmitting a light beam, a holding member whose holding member holds the channel with the end of the channel being exposed from the surface, electric wiring formed on the surface, an optical semiconductor element, mounted above the surface, including an active area to emit or receive a light beam and an electrode pad electrically connected to the electric wiring, the active area optically coupled to the waveguide at the end of the channel, and an electrical insulation film between the optical semiconductor element and the holding member, including openings each corresponding to an electrical connection between the electrode pad and the electric wiring, and an optically coupling portion between the active area and the waveguide, the electrical insulation film being in contact with a portion of the end of the channel.
    Type: Application
    Filed: July 26, 2004
    Publication date: March 24, 2005
    Inventors: Hiroshi Hamasaki, Hideto Furuyama, Hideo Numata, Takashi Imoto
  • Patent number: 6861738
    Abstract: There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Oyama, Mitsuyoshi Endo, Chiaki Takubo, Takashi Yamazaki, Takashi Imoto
  • Publication number: 20040105117
    Abstract: To realize a mechanism for executing an optimum cancelling method among a plurality of cancelling methods for many various print environments on the user side, there is provided a mechanism having means for obtaining limitation information of the cancellation, using the optimum cancelling method among the plurality of cancelling methods on the basis of the obtained limitation information of the cancellation, and executing it.
    Type: Application
    Filed: August 26, 2003
    Publication date: June 3, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideki Honda, Takashi Imoto
  • Patent number: 6734541
    Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: May 11, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
  • Patent number: 6617678
    Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamazaki, Mitsuyoshi Endo, Chiaki Takubo, Katsuhiko Oyama, Takashi Imoto, Mikio Matsui
  • Publication number: 20020195698
    Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.
    Type: Application
    Filed: May 16, 2002
    Publication date: December 26, 2002
    Inventors: Takashi Yamazaki, Mitsuyoshi Endo, Chiaki Takubo, Katsuhiko Oyama, Takashi Imoto, Mikio Matsui
  • Publication number: 20020190368
    Abstract: A semiconductor laminated module comprises a plurality of unit packages in which semiconductor chips are bonded to base substrates with a first adhesive, a second adhesive to form a laminated body by bonding the plurality of unit packages to each other, a third adhesive formed to cover an upper surface of the semiconductor chips and having substantially the same thermal expansion coefficient as that of the first adhesive, and an uppermost substrate bonded to uppermost one of the unit packages with the second adhesive.
    Type: Application
    Filed: June 18, 2002
    Publication date: December 19, 2002
    Applicant: KABUSHIKI KAISHI TOSHIBA
    Inventors: Hiroshi Shimoe, Naohisa Okumura, Takashi Imoto, Ryuji Hosokawa
  • Publication number: 20020180030
    Abstract: There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 5, 2002
    Applicant: KABUSHIKI KAISHA TOAHIBA
    Inventors: Katsuhiko Oyama, Mitsuyoshi Endo, Chiaki Takubo, Takashi Yamazaki, Takashi Imoto
  • Patent number: 6469374
    Abstract: A semiconductor device including superposed packages is disclosed, which comprises an superposed structure formed by superposing a plurality of superposed substrates each comprised of a wiring printed substrate loaded with a semiconductor element and a conductive-via provided insulating substrate, wherein the wiring printed substrate has a plurality of contact electrodes formed in a plurality of via holes and a plurality of wiring conductors electrically connected to the contact electrodes, the semiconductor element is electrically connected to wiring conductors provided on the wiring printed substrate, the insulating substrate includes a chip cavity larger than the semiconductor element size for accommodating the semiconductor element loaded on the wiring printed substrate and a plurality of contact electrodes, the conductive-via provided insulating substrate and the wiring printed substrate are superposed in such a manner that the contact electrode in the conductive-via provided insulating substrate and the
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: October 22, 2002
    Assignees: Kabushiki Kaisha Toshiba, Ibiden Co., Ltd.
    Inventor: Takashi Imoto
  • Publication number: 20020021453
    Abstract: A printing apparatus which quickly cancels a print job without any influence on the subsequent other print jobs when a print cancel instruction is issued. During printing, if a print cancel instruction is inputted from a printer operation unit 107, a printer function manager 109 notifies a print command interpreter 108 of the cancellation. The print command interpreter 108 searches data processed at that time in a transmission/reception buffer for an end mark command indicating the end of the cancelled job. Then the print command interpreter 108 deletes the data before the end mark command.
    Type: Application
    Filed: July 13, 2001
    Publication date: February 21, 2002
    Inventors: Kazuya Sakamoto, Takayuki Fujita, Tsutomu Takahashi, Mikio Shiga, Hiroshi Maruoka, Tetsuya Kawanabe, Nobuo Onuma, Masao Maeda, Nobuhiro Saito, Shunichi Kunihiro, Takashi Imoto, Kazuhisa Ebuchi