Patents by Inventor Takashi Inoue

Takashi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601609
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: March 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Patent number: 9594245
    Abstract: An adaptive optics system includes a spatial light modulator configured to spatially modulate a phase of an optical image incident on a modulation surface and a wavefront sensor including a lens array having a plurality of two-dimensionally arranged lenses and an optical detection element for detecting a light intensity distribution including converging spots formed by the lens array and configured to receive the optical image after the modulation from the spatial light modulator, and compensates for wavefront distribution by controlling a phase pattern displayed in the spatial light modulator based on a wavefront shape of the optical image obtained from the light intensity distribution, wherein a correspondence relation between the modulation surface and the wavefront sensor is adjusted.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: March 14, 2017
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hongxin Huang, Takashi Inoue
  • Publication number: 20170054014
    Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Application
    Filed: November 8, 2016
    Publication date: February 23, 2017
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20170031158
    Abstract: In an aberration-correcting method according to an embodiment of the present invention, in an aberration-correcting method for a laser irradiation device 1 which focuses a laser beam on the inside of a transparent medium 60, aberration of a laser beam is corrected so that a focal point of the laser beam is positioned within a range of aberration occurring inside the medium. This aberration range is not less than n×d and not more than n×d+?s from an incidence plane of the medium 60, provided that the refractive index of the medium 60 is defined as n, a depth from an incidence plane of the medium 60 to the focus of the lens 50 is defined as d, and aberration caused by the medium 60 is defined as ?s.
    Type: Application
    Filed: October 11, 2016
    Publication date: February 2, 2017
    Inventors: Haruyasu ITO, Naoya MATSUMOTO, Takashi INOUE
  • Publication number: 20170030776
    Abstract: A waveform measurement device includes an input spectrum acquisition unit for acquiring an input intensity spectrum being an intensity spectrum of pulsed light, an optical element inputting the pulsed light and outputting light having an intensity spectrum corresponding to a phase spectrum of the pulsed light, an output spectrum acquisition unit for acquiring an output intensity spectrum being an intensity spectrum of the light output from the optical element, and a phase spectrum determination unit for determining the phase spectrum of the pulsed light by comparing an output intensity spectrum calculated when the pulsed light having an input intensity spectrum and a virtual phase spectrum is assumed to be input to the optical element with the output intensity spectrum acquired in the output spectrum acquisition unit. The phase spectrum determination unit sets the virtual phase spectrum by deforming the control phase spectrum.
    Type: Application
    Filed: April 8, 2015
    Publication date: February 2, 2017
    Inventors: Takashi INOUE, Koyo WATANABE, Koji TAKAHASHI, Naoya MATSUMOTO
  • Patent number: 9559183
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Publication number: 20170005189
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a third semiconductor layer formed over the second semiconductor layer, a gate electrode formed over the third semiconductor layer, and a gate insulating film formed between the third semiconductor layer and the gate electrode. The second semiconductor layer includes an Aly?1-yN layer (? includes Ga or In, and 0?y<1), and the third semiconductor layer includes an Alz?1-zN layer (0?z<1). y of the Aly?1-yN layer forming the second semiconductor layer increases from the third semiconductor layer to the first semiconductor layer at least in a region under the gate electrode. There is a relationship “z>y” at an interface between the second nitride semiconductor layer and the third nitride semiconductor layer.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
  • Patent number: 9536978
    Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 3, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue
  • Patent number: 9530879
    Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
  • Patent number: 9519127
    Abstract: A zoom lens includes a first lens unit including one of an SLM or a VFL, a second lens unit being optically coupled between the first lens unit and a focal plane and including one of an SLM or a VFL, and a control unit controlling focal lengths of the first and second lens units. A distance between the first lens unit and the second lens unit and a distance between the second lens unit and the focal plane are invariable. The control unit changes a magnification ratio of the zoom lens by changing the focal lengths of the first and second lens units.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 13, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Naoya Matsumoto, Takashi Inoue, Yuu Takiguchi
  • Patent number: 9520489
    Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 13, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Patent number: 9519141
    Abstract: An adaptive optics system includes a spatial light modulator configured to spatially modulate a phase of an optical image incident on a modulation surface including N two-dimensionally arranged regions and a wavefront sensor including a lens array having N two-dimensionally arranged lenses corresponding to the N regions and an optical detection element for detecting a light intensity distribution including M converging spots formed by the lens array and configured to receive the optical image after the modulation from the spatial light modulator, and compensates for the wavefront distortion by controlling a phase pattern displayed in the spatial light modulator based on a wavefront shape of the optical image obtained from the light intensity distribution, wherein a correspondence relation between the region of the spatial light modulator and the converging spot formed in the wavefront sensor is specified while the compensation for the wavefront distortion is executed.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: December 13, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hongxin Huang, Takashi Inoue
  • Publication number: 20160347312
    Abstract: A vehicle speed limiter system installed on a vehicle includes a detection unit to detect a speed limit value of a road while the vehicle is traveling; a setting unit to set the speed limit value; a limiter unit to limit the vehicle speed, based on the speed limit value; an obtainment unit to obtain a stepping amount on an accelerator pedal; a calculation unit to calculate a parameter depending on the stepping amount in a state where the vehicle speed is being limited by the limiter unit; and a display unit to display information based on the parameter, in a case where a speed limit value newly detected by the detection unit is greater than the speed limit value previously set by the setting unit, before the setting unit sets the speed limit value newly detected.
    Type: Application
    Filed: April 4, 2016
    Publication date: December 1, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Nobuyuki TOMATSU, Takashi INOUE, Sokfan YEE, Tetsuya TAIRA, Keiji YAMASHITA, Takato MASUDA
  • Publication number: 20160347175
    Abstract: A vehicle's accelerator pedal depression amount is detected; a speed limit of a road on which the vehicle is traveling is determined; a start of a lane change is estimated; an upper-limit speed is determined each time when the speed limit changes; and the travelling speed is controlled to not exceed the upper-limit speed even if the accelerator pedal depression amount increases to cause the speed of the vehicle to exceed the upper-limit speed. The speed of the vehicle is controlled, until a predetermined timing, to not exceed the upper-limit speed determined before the start of a lane change is estimated, if (i) the start of a lane change is estimated, and (ii) a reduction in the speed limit is determined. After the predetermined timing, the speed of the vehicle is controlled to not exceed the currently determined upper-limit speed.
    Type: Application
    Filed: April 20, 2016
    Publication date: December 1, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji YAMASHITA, Takashi INOUE, Tetsuya TAIRA, Takato MASUDA, Nobuyuki TOMATSU, Sokfan YEE
  • Publication number: 20160347313
    Abstract: A control system for a vehicle includes an imaging device; a co-ECU to limit the travel speed of the vehicle; and an ECU to set the speed limit, that recognizes the speed limit value on a road while traveling, and sets the recognized speed limit value in the co-ECU. If the elapsed time since the speed limit value has been set reaches a predetermined time, the ECU estimates the speed limit value on the road while traveling, and if receiving a switch command, switches the speed limit value set in the co-ECU to the estimated speed limit value so as to avoid limiting the vehicle speed by a speed limit value that is different from the actual speed limit value on the road.
    Type: Application
    Filed: May 19, 2016
    Publication date: December 1, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi INOUE, Sokfan YEE, Tetsuya TAIRA, Keiji YAMASHITA, Nobuyuki TOMATSU, Takato MASUDA
  • Publication number: 20160349496
    Abstract: A control apparatus includes a lens, an SLM presenting a modulation pattern on a modulation plane and outputting modulated light L2 for forming light spots P1 and P2 on a pupil plane of the lens, an imaging device imaging a fringe pattern image formed on a focal plane of the lens and generating image data Da indicating the fringe pattern image, a calculation unit calculating at least one kind of parameter among an intensity amplitude, a phase shift amount, and an intensity average from the image data Da, an analysis unit obtaining a deviation in relative positions of an optical axis of the lens and a reference coordinate of the modulation plane based on the parameter, and a changing unit changing an origin position of the reference coordinate so that the deviation in the relative positions is decreased.
    Type: Application
    Filed: May 25, 2016
    Publication date: December 1, 2016
    Inventors: Koyo WATANABE, Takashi INOUE
  • Publication number: 20160339913
    Abstract: A vehicle speed limiting apparatus includes an opening detection unit to detect an opening of an accelerator pedal of the vehicle; an estimation unit to estimate whether the vehicle starts a lane change; and an ECU to implement an upper-limit setting unit to set an upper-limit speed of the vehicle, a vehicle speed control unit to control the traveling speed so as not to exceed the upper-limit speed even when the opening of the accelerator pedal becomes great enough to make the traveling speed exceed the upper-limit speed, and a permissible speed setting unit to set a permissible speed higher than the upper-limit speed. When the estimation unit estimates that the vehicle starts the lane change, the vehicle speed control unit permits the traveling speed to exceed the upper-limit speed, and controls the traveling speed so as not to exceed the permissible speed.
    Type: Application
    Filed: May 19, 2016
    Publication date: November 24, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keiji YAMASHITA, Takashi INOUE, Tetsuya TAIRA, Takato MASUDA, Nobuyuki TOMATSU, Sokfan YEE
  • Patent number: 9502551
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
  • Patent number: 9492842
    Abstract: Provided is: a cell culture membrane, which is free from materials derived from living organisms, can easily be industrially mass-produced, exhibits superior long-term storage properties and chemical resistance, has excellent cell adhesion properties and long-term culture properties and is capable of replicating a cell adhesion morphology that is similar to that of collagen derived from living organisms and being used for conventional cell cultivation. Also provided are a cell culture substrate, and a method for manufacturing the cell culture substrate. In the present invention, as a cell adhesion layer, a polymer membrane represented by formula (I) is formed on the base of a cell culture substrate so as to have a membrane thickness equal to or greater than 0.2 ?m (in the formula, R1 and R2 represent a —(CH2)n—NH2 moiety (n is an integer of 1-10 inclusive.) or H, with at least one of R1 and R2 being a —(CH2)n—NH2 moiety. Moreover, l and m are positive integers expressing polymerization degree).
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: November 15, 2016
    Assignees: KISCO LTD., DAISANKASEI CO., LTD., The University of Tokyo
    Inventors: Yasuo Yoshimoto, Kentaro Kamimae, Yuki Tanabe, Taku Oguni, Takashi Inoue, Tsutomu Mochizuki, Makoto Hirama, Teruo Fujii, Hiroshi Kimura, Hideto Tozawa
  • Patent number: D775607
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 3, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Katsuyoshi Uchiyama, Takashi Inoue, Kenji Miyata