Abstract: A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality of word lines each connected to the memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspondence to each word line to store occurrences of activation of the word line to read out data from the memory cells.

Abstract: A semiconductor integrated circuit device is provided, which includes a semiconductor layer formed via an embedded insulation film on a substrate and an FBC (Floating Body Cell) which stores data by accumulating a majority carrier in a floating channel body formed on the semiconductor layer.

Abstract: A semiconductor storage device comprises memory cells that store data by accumulating or releasing an electric charge; a memory cell array having a matrix arrangement of the memory cells; a plurality of word lines connected to memory cells aligned on rows of the memory cell array; a plurality of sub-bit lines connected to memory cells aligned on columns of the memory cell array; a bit line select circuit selecting the sub-bit line of a column; a main bit line connected to the sub-bit line selected by the bit line select circuit; a sense line detecting the potential of the sub-bit line selected by the bit line select circuit via the main bit line and reading data out of the memory cell; a write driver applying a voltage to the sub-bit line selected by the bit line select circuit via the main bit line and writing data into the memory cell; and a first switching element connected to the main bit line and turning on when the current flowing in the memory cell is detected externally via the sub-bit line without th

Abstract: A discharge bulb ballast has a control circuit (11) that includes a turning point detecting unit (101) for detecting a turning point at which a bulb voltage starts rising after switching on a discharge bulb (7). Immediately after switching on the discharge bulb (7), a power control unit (102) carries out control in such a manner that the discharge bulb (7) is supplied with first power. When the turning point detecting unit (101) detects that the voltage of the discharge bulb (7) exceeds the turning point, the power control unit (102) supplies the discharge bulb (7) with second power less than the first power.

Abstract: A semiconductor memory device includes memory cell arrays; bit lines; word lines; a column selection line; and a sense amplifier comprising a first sense node connected to the first bit line, a second sense node connected to the second bit line, a first cross couple including two switching elements of first conduction type connected in series between the first sense node and the second sense node, and a second cross couple including two switching elements of second conduction type connected in series between the first sense node and the second sense node, a first node between the two switching elements in the first cross couple and a second node between the two switching elements in the second cross couple being connected to different power supplies via a plurality of routes, the sense amplifier selecting the routes on the basis of a potential on the column selection line.

Abstract: A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, said memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of said memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of said memory cell lines aligned in a channel widthwise direction of the memory cells, wherein said memory cells on a common memory cell line are aligned to uniformly orient the directions from their s

Abstract: A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, said memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of said memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of said memory cell lines aligned in a channel widthwise direction of the memory cells, wherein said memory cells on a common memory cell line are aligned to uniformly orient the directions from their s

Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

Abstract: A discharge lamp starter includes a DC/DC converter. The DC/DC converter includes a forward section for producing a first output voltage that is determined by a power supply voltage and a turn ratio of a transformer, and a flyback section for producing a second output voltage that is determined by an inductance of a primary winding of the transformer and a current flowing through the primary winding. The DC/DC converter generates its output voltage by adding the first output voltage and the second output voltage. The configuration can reduce the size of the discharge lamp starter.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A semiconductor memory comprises a semiconductor substrate including a semiconductor film on a first insulating film; a memory cell that stores data by charging or discharging a body region formed in said semiconductor film, the memory cell including a source layer on one side of said body region and a drain layer on another side of said body region; a memory cell array in which a plurality of said memory cells are arranged in a matrix; a second insulating film provided on said body region of said memory cell; a first word line provided on said second insulating film; a bit line connected to the drain layer of said memory cell, and having a reference potential when said memory cell is in a data retaining state; a source line connected to the source layer of said memory cell, and having the reference potential; and a second word line buried in said first insulating film, and provided below said body region of said memory cell, wherein a potential VBWLH of said second word line when said memory cell is in the d

Abstract: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

Abstract: A semiconductor memory comprises a semiconductor substrate including a semiconductor film on a first insulating film; a memory cell that stores data by charging or discharging a body region formed in said semiconductor film, the memory cell including a source layer on one side of said body region and a drain layer on another side of said body region; a memory cell array in which a plurality of said memory cells are arranged in a matrix; a second insulating film provided on said body region of said memory cell; a first word line provided on said second insulating film; a bit line connected to the drain layer of said memory cell, and having a reference potential when said memory cell is in a data retaining state; a source line connected to the source layer of said memory cell, and having the reference potential; and a second word line buried in said first insulating film, and provided below said body region of said memory cell, wherein a potential VBWLH of said second word line when said memory cell is in the d

Abstract: A semiconductor memory device includes: a device substrate having a semiconductor layer separated by a dielectric layer from a base substrate; a memory cell array having a plurality of memory cells formed and arranged on the semiconductor layer of the device substrate, each the memory cell having a MOS transistor structure with a body in an electrically floating state to store data based on a majority carrier accumulation state of the body; and a sense amplifier circuit configured to read out data of a selected memory cell in the memory cell array to store the read data in a data latch, then transfer the read data to an output circuit and write back the read data into the selected memory cell.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: a cell array including a plurality of memory cells, each being connected to bit lines and word lines arranged in a row direction and a column direction; and a sense amplifier which controls read-out of data stored in the memory cells, wherein the sense amplifier includes: a pair of sense nodes provided corresponding to a pair of the bit lines; a connection switching circuit connected between the pair of bit lines and the pair of sense nodes, which connects electrically the pair of bit lines and the pair of sense nodes when a write control signal is in a prescribed logic level; and a timing control circuit which sets the write control signal to the prescribed logic level substantially at the same time as a timing when a column selection signal selects a column to which the memory cell to be written is connected during data writing period for the memory cells, and holds the write control signal to the prescribed

Abstract: A ballast for a vehicle metal halide lamp is simplified using a DC-AC one-step-boost high frequency ballast system. To satisfy requirements specific to a metal halide lamp, a discharge developing capacitor is installed on a primary side of a transformer in parallel with a DC power supply, ensuring discharge development after a breakdown. To reduce the size and increase the operating voltage of the transformer, a booster circuit and voltage-doubler circuit are installed on the primary side and secondary side of the transformer, respectively. To reduce the size of the transformer and achieve a stable discharge, the ballast frequency is swept within a range between the specified minimum frequency and maximum frequency so that the center frequency is from 80 kHz to 120 kHz, and the same frequency is unsustained for more than 10 msec.

Abstract: In an ultrasonic wave utilizing device having a cylindrical elastic holder 2 into which an ultrasonic sensor 3 is pressed and a cylindrical part 23 that is closed at one end and is formed in a case 1 in such a way as to have this elastic holder 2 assembled therein, the elastic holder 2 has an elastic end wall 33 formed at an end of pressing side, a first elastic retaining part 35 for retaining the outside end edge of the cylinder part of the pressed-into ultrasonic sensor 3, and a second elastic retaining part 36, 37.