Abstract: The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the memory cells disposed in a matrix; a plurality of word lines connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers detecting data within the memory cells by using an average value of electric characteristics of the dummy cells that store mutually different digital data as a reference signal; and a plurality of switching elements electrically connecting four or more of the bit lines in order to generate the reference signal.

Abstract: This disclosure concerns a semiconductor memory device including a memory cell including a floating body in an electrically floating state and storing therein data according to number of a plurality of majority carriers accumulated in the floating body; a dummy cell generating a reference signal based on which the data stored in the memory cell is detected; a word line connected to a gate of the memory cell; a dummy word line connected to a gate of the dummy cell; a bit line connected to a source or a drain of the memory cell and a source or a drain of the dummy cell; and a diffused layer adjacent to the source or the drain of the dummy cell, the diffused layer being equal in conduction type to the floating body of the dummy cell, wherein the floating body of the dummy cell, the source or the drain of the dummy cell, and the diffused layer constitute a bipolar transistor.

Abstract: The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a plurality of bit lines connected to drain diffusion regions of the transistors, one of the bit lines being connected to the sense amplifier. The first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the semiconductor layer. The second data state is a state in which a forward bias is applied between the semiconductor layer and the drain diffusion region to extract the excessive majority carriers from within the semiconductor layer to the drain diffusion region.

Abstract: This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing into the memory cells is requested.

Abstract: A discharge lamp lighting apparatus includes: a DC power supply to supply power to a HID lamp; a transformer to transmit a voltage of DC power supply to the HID lamp; a switch connected between the DC power supply and a primary winding of the transformer; switches connected to a primary side of the transformer; an inductance connected in series to a secondary winding of the transformer; a series resonance circuit connected to a secondary side of the transformer and including an inductance and a capacitor; and a parallel resonance circuit connected to the secondary side of the transformer and including an inductance and a capacitor. The switches are opened or closed to intermittently supply power from the DC power source to the transformer to always supply a current to the transformer.

Abstract: A semiconductor integrated apparatus, including: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET; an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.

Abstract: A semiconductor memory device includes: a semiconductor layer which is formed on an insulating layer; a plurality of transistors which are formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs which are connected to the source regions of the transistors; drain contact plugs which are connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs; and bit lines which are formed so as to cross the word lines and which are connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Abstract: The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.

Abstract: A semiconductor memory device includes a memory cell including a floating body region in an electrically floating state and storing data by accumulating or discharging charges in or from the floating body region; a memory cell array including a plurality of the memory cells; a word line connected to a gate of the memory cell; a bit line connected to a diffusion layer of the memory cell; a sense amplifier connected to the bit line; and a decoder applying a first potential to the word line when data “1” is written to the memory cell and applying a second potential different from the first potential to the word line when data “0” is written to the memory cell.

Abstract: A semiconductor memory device includes a memory cell including a floating body; a word line connected to a gate of the memory cell; a data bit line connected to the memory cell and transmitting the data stored in the memory cell; a reference bit line transmitting a reference voltage; a data sense node connected to the data bit line and transmitting the data in the memory cell; a reference sense node connected to the reference bit and transmitting the reference voltage; a plurality of transfer gates connected between the data bit line and the data sense node and between the reference bit line and the reference sense node, respectively; and a current load circuit connected to each of the data sense node and the reference sense node and constituted by a transistor equal in conduction type to the memory cell.

Abstract: A semiconductor storage device includes a semiconductor substrate; an sulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, the memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of the memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of the memory cell lines aligned in a channel widthwise direction of the memory cells.

Abstract: First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

Abstract: A headlight optical axis control unit of a vehicle capable of reducing cost, improving accuracy and ensuring safety is provided. An inclination angle detecting sensor placed in the front of a vehicle is connected to a control unit, and includes two transceivers of ultrasonic sensors. The two transceivers obtain the levels at their locations from the phase differences between the emitted waves and the reflected waves from a road surface, and measure the inclination angle from the level differences. The inclination angle is continuously detected during running of the vehicle. The measured values of the inclination angle are subjected to the cumulative sum and cumulative averaging. According to the average value, the control unit adjusts the angle of the optical axis of the headlights via headlight optical axis control sections.

Abstract: A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation, the number of times of activation being read from the counter cell array; a counter buffer circuit temporarily storing the number of times of activation and writing back the incremented number of times of activation to the counter cell array; and a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation reaches a predetermined value.

Abstract: A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell.

Abstract: An image processing apparatus relating to the present invention outputs a document, which a user has commanded for output, and includes a rule storage section that stores an approval rule to determine a document which requires approval to be output, and information of an authorizer who determines whether or not to give approval, and an output control section that performs a control operation so that the document is not output until the authorizer approves the output of the document, when the document which is a target of the instruction of output is the document which requires approval to be output.

Abstract: A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.

Abstract: A semiconductor storage device according to one embodiment of the present invention, comprising: FBCs (Floating Body Cells) which store data by accumulating a majority carrier in a floating channel body; and sense amplifiers which perform control reading out data stored in said FBC, wherein each of said sense amplifier includes: a pair of sense nodes provided corresponding to a bit line pair to which said FBC is connected; a pair of load which flow currents through said pair of sense nodes; latch circuits which latch potentials of said pair of sense nodes when a potential difference between said pair of sense nodes reaches a predetermined value; and an output control circuit which outputs latched outputs of said latch circuits at a predetermined timing and feeds back the latched outputs to said bit line pair side to again write it into said FBC.

Abstract: A primary side current detecting resistor 5 detects a primary side current value divided from a DC power supply 1 to the primary side of a DC power supply circuit 2, an output current detecting resistor 6 detects an output current value split into an inverter circuit 3 onward, a total current detector 7 detects a total current value flowing to a plurality of load circuits such as the DC power supply circuit 2 and the inverter circuit 3 from the current values detected, and a controller 8 controls the output power by controlling a switching transistor 24 of the DC power supply circuit 2 in response to the total current value detected, thereby controlling the current Ib fed from the DC power supply 1.