Abstract: This disclosure concerns a memory comprising a memory cell including a floating body provided between a source and a drain and storing therein data according to number of majority carriers accumulated in the floating body; a word line connected to a gate of the memory cell; a bit line connected to the drain of the memory cell; a source line connected to the source of the memory cell; a sense amplifier sensing data from the memory cell selected by the bit line and the word line; a driver applying a voltage to the word line to form a channel in the memory cell and shifting a voltage of the source line in a voltage direction opposite to a transition direction of the voltage of the word line when first data indicating that the number of the majority carriers is small is written to the memory cell.

Abstract: A DC/DC converter device according to the present invention includes a plurality of resonant DC/DC converters 3, connected in parallel, and a timing control circuit 5 driving the plurality of resonant DC/DC converters at substantially the same frequency with a phase shift.

Abstract: This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.

Abstract: A single DC/DC converter section 2 has two circuits connected in parallel: a flyback type boosting circuit 2A and a boosting circuit 2B. The former includes a transformer 2a and a switching device 2b and the like to boost DC voltage of a DC power supply 1, and the latter includes a transformer 2d and a switching device 2e and the like to do likewise. A control section 4 carries out switching control of the switching devices 2b and 2e in such a manner that shifts from each other the phases of current Ida and current Idb to be supplied from the two boosting circuits 2A and 2B to a plurality of LED 3a and the like connected in series in a light emitting section 3.

Abstract: This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the memory cell to transmit the data; a second bit line transmitting reference data used to detect the data stored in the memory cell; a first sense node and a second sense node transmitting the data stored in the memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop applying a load current to the memory cell during a data read operation and amplifying a potential difference generated between the first sense node and the second sense node by turning off the first short-circuiting switch.

Abstract: A semiconductor memory device including a memory cell including a floating body in an electrically floating state and storing therein data according to number of a plurality of majority carriers accumulated in the floating body; a dummy cell generating a reference signal based on which the data stored in the memory cell is detected; a word line connected to a gate of the memory cell; a dummy word line connected to a gate of the dummy cell; a bit line connected to a source or a drain of the memory cell and a source or a drain of the dummy cell; and a diffused layer adjacent to the source or the drain of the dummy cell, the diffused layer being equal in conduction type to the floating body of the dummy cell, wherein the floating body of the dummy cell, the source or the drain of the dummy cell, and the diffused layer constitute a bipolar transistor.

Abstract: A document monitor device, which includes: a confidential information storage section that stores confidentiality level information of documents managed in a document management device associated with identification information of each of the documents; a feature storage section that stores features of the documents associated with the identification information; a selection section that selects a target document from the managed documents based on the confidentiality level information; an acquisition section that acquires a target image to be processed by an image processing device; an extraction section that extracts features of the target image; a similarity level calculation section that calculates a similarity level between the features stored in association with the identification information of the selected target document and the extracted features; and a detection information output section that, when the similarity level is a prescribed value or over, outputs information indicating that a similar im

Abstract: A high-voltage generating transformer for a discharge lamp lighting apparatus according to the present invention includes a rodlike core; a secondary winding bobbin that is divided into a plurality of sections, and where the core is disposed in the central portion thereof; a secondary winding part wound on the secondary winding bobbin, divided between the plurality of sections of the bobbin; a primary winding bobbin disposed around the outer periphery of the secondary winding part; and a primary winding part wound on the primary winding bobbin; wherein the primary winding bobbin is changed in thickness every section or every plurality of sections of the second winding part such that the bobbin has a thickened thickness on the side where the potential difference between the primary winding part and the secondary winding part is high, and the bobbin has a thinned thickness on the side where the potential difference is low.

Abstract: A capacitor 42 (C1) of a first bootstrap circuit 4 for maintaining the ON state of a first switching device 61, one of the two switching devices disposed on a higher potential side of first DC voltage V1, is not only charged with second DC voltage V2, but also supplied with a charging current from third DC voltage V3 on a secondary winding n2 side of a transformer 22, and maintains the ON state of the first switching device 61 for a long time with the charge of both of them. This makes it possible to fix the polarity of the voltage to be applied to the discharge lamp 8 to the single side polarity closer to the DC output operation.

Abstract: This disclosure concerns a method of driving a memory including memory cells, bit lines, and word lines, each memory cell having a source, a drain, and a floating body, the method comprising performing a refresh operation for recovering deterioration of first logical data of the memory cells and deterioration of second logical data of the memory cells, wherein in the refresh operation, the number of the carriers injected into the floating body is larger than the number of the carriers discharged from the floating body when a potential at the floating body is larger than a critical value, and the number of the carriers injected into the floating body is smaller than the number of the carriers discharged from the floating body when the potential at the floating body is smaller than the critical value.

Abstract: This disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data; bit lines and word lines connected to the memory cells; sense amplifiers connected to the bit lines; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells; and a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode, and setting the refresh interval to a second interval longer than the first interval in a data retention mode, the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device, the data write mode being a mode in which data from the outside is written to the selected memory cell.

Abstract: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: The disclosure concerns a semiconductor memory device includes a memory cell array including memory cells; word lines; bit lines; a counter cell array including counter cells provided corresponding to the word lines and storing the number of times of activating the word lines; an adder incrementing the number of times of activating the word lines which is read out from the counter cell array, when data is read or written in the memory cell; a counter buffer circuit temporarily storing the number of times of activating the word lines, and writing back the incremented number of times of activating the word lines into the counter cell array; and a sense amplifier executing a refresh operation during a data read cycle or a data write cycle, when the number of times of activating one of the word lines has reached a predetermined value.

Abstract: A discharge lamp ballast apparatus has a reflecting mirror 2 and a power source circuit 5. The reflecting mirror 2 is disposed around a discharge light bulb 1 in such a manner as to cast light from the discharge light bulb 1 in one direction. The power source circuit 5 applies a start pulse of a negative potential with respect to the potential of the reflecting mirror 2 to an electrode 6 located at a side with the higher electric field concentration produced between electrodes 6 and 7 to which a high voltage of the start pulse is applied. This makes it possible to produce a dielectric breakdown near the electrode 6, and makes it easier to start the discharge light bulb 1.

Abstract: This disclosure concerns a semiconductor memory including memory cells; a first dummy cell and a second dummy cell generating a reference potential and storing first data and second data of mutually opposite polarities, respectively; word lines; a first and a second dummy word lines connected to gates of the first and the second dummy cells; a pair of bit lines; and a sense amplifier provided for the pair of bit lines, the sense amplifier detecting the first data using the second data as a reference or detecting the second data using the first data as a reference in a refresh operation of the first and the second dummy cells.

Abstract: This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

Abstract: A semiconductor memory device includes a semiconductor substrate including a semiconductor layer on a first insulation film; a memory cell including a source and a drain formed in the semiconductor layer, and a floating body region provided between the source and the drain, the memory cell storing data according to an amount of charges accumulated in the floating body region; a second insulation film provided on the floating body region of the memory cell; a word line provided on the second insulation film; a bit line connected to the drain; a source line connected to the source; and a plate electrode electrically insulated from the floating body region by the first insulation film, wherein in at least a part of a period for writing data to the memory cell, a potential of the plate electrode is changed to reduce an absolute value of a threshold voltage of the memory cell.

Abstract: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.