Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing into the memory cells is requested.

Abstract: This disclosure concerns a memory comprising memory cells including floating bodies, logic data being stored in the memory cells; word lines connected to gates of the memory cells; bit lines connected to the memory cells; and sense amplifiers connected to the bit lines, and applying a first voltage to the bit lines when first logic data is written to the memory cells connected to the bit lines, wherein the sense amplifiers apply a second voltage to the memory cells having stored therein the first logic data during a refresh operation in which at least second logic data stored in the memory cells is recovered, the second logic data is opposite in logic to the first logic data, and the second voltage is lower in absolute value than the first voltage and equal to or higher in absolute value than a potential of sources of the memory cells.

Abstract: This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.

Abstract: A semiconductor storage device according to the present invention, comprising: a first semiconductor layer formed on a substrate via a buried insulation layer; an FBC (Floating Body Cell) having a channel body of floating type formed on the first semiconductor layer, a main gate which forms a channel at a first face side of the channel body, and an auxiliary gate formed to capacitively couple on a second face at an opposite side of the first face; a logic circuit formed on the first semiconductor layer, separate from the FBC by an insulation film, which transfers a signal for the FBC; a second semiconductor layer which locates below the FBC and is formed along an under face of the buried insulation film; and a third semiconductor layer which locates below the logic circuit and is formed along an under face of the buried insulation film, wherein the second and third semiconductor layers are set to be in a potential different from each other.

Abstract: This disclosure concerns a semiconductor memory device comprising Fin semiconductors extending in a first direction; source layers provided in the Fin semiconductors; drain layers provided in the Fin semiconductors; floating bodies provided in the Fin semiconductors between the source layers and the drain layers, the floating bodies being in an electrically floating state and accumulating or discharging carries so as to store data; first gate electrodes provided in first grooves located between the Fin semiconductors adjacent to each other; second gate electrodes provided in second grooves adjacent to the first grooves and located between the Fin semiconductors adjacent to each other; bit lines connected to the drain layers, and extending in a first direction; word lines connected to the first gate electrodes, and extending in a second direction orthogonal to the first direction; and source lines connected to the source layers, and extending in the second direction.

Abstract: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

Abstract: A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

Abstract: A semiconductor storage apparatus including cell arrays, each having a plurality of memory cells connected to a pair of first and second bit lines; and sense amplifiers, each being provided corresponding to the pair of first and second bit lines and sensing data read out from the memory cell to be read out, wherein each of the sense amplifiers includes a current mirror circuit having first and second current paths connected directly or indirectly to the pair of first and second bit lines; and the current mirror circuit includes: a first transistor which has a source and a drain short-circuited to each other and flows a reference current between the source and the drain; and a second transistor, of which gate is commonly connected to a gate of the first transistor, and which flows a current passing through the memory cell to be read out between a source and a drain thereof.

Abstract: This disclosure concerns a memory comprising a memory cell including a floating body provided between a source and a drain and storing therein data according to number of majority carriers accumulated in the floating body; a word line connected to a gate of the memory cell; a bit line connected to the drain of the memory cell; a source line connected to the source of the memory cell; a sense amplifier sensing data from the memory cell selected by the bit line and the word line; a driver applying a voltage to the word line to form a channel in the memory cell and shifting a voltage of the source line in a voltage direction opposite to a transition direction of the voltage of the word line when first data indicating that the number of the majority carriers is small is written to the memory cell.

Abstract: A semiconductor memory device includes a memory cell including a floating body; a word line connected to a gate of the memory cell; a data bit line connected to the memory cell and transmitting the data stored in the memory cell; a reference bit line transmitting a reference voltage; a data sense node connected to the data bit line and transmitting the data in the memory cell; a reference sense node connected to the reference bit line and transmitting the reference voltage; a plurality of transfer gates connected between the data bit line and the data sense node and between the reference bit line and the reference sense node, respectively; and a current load circuit connected to each of the data sense node and the reference sense node and constituted by a transistor equal in conduction type to the memory cell.

Abstract: A through hole that is slightly larger than a size of a rear end of a transformer container is formed in a rear cover constituting a part of an external wall of a starting circuit unit. The transformer container houses therein a transformer and constitutes a transformer portion. The transformer portion is assembled such that a rear end of the transformer container projects from the through hole. This allows the transformer container to constitute a part of the external wall of the starting circuit unit.

Abstract: A semiconductor memory device includes a memory cell including a floating body region and storing data on the basis of the amount of charges in the floating body region; word lines; a counter cell array including counter cells provided to correspond to the word lines, the counter cell array storing the number of times of activation of the word lines; an adder incrementing the number of times of activation, the number of times of activation being read from the counter cell array; a counter buffer circuit temporarily storing the number of times of activation and writing back the incremented number of times of activation to the counter cell array; and a refresh request circuit outputting an instruction to execute a refresh operation to the memory cells connected to the word line when the number of times of activation reaches a predetermined value.

Abstract: This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to the gates of the memory cells; bit lines connected to the drains of the plurality of memory cells; sense amplifiers detecting data stored in the memory cells via the bit lines, the sense amplifiers writing data to the memory cells via the bit lines and latching read data or data to be written; and a plurality of transfer gates connecting or disconnecting the sense amplifiers to or from the bit lines, in a period of a serial access for continuously writing the data to the memory cells connected to an activated word line among the word lines, the transfer gates connecting the sense amplifiers to the bit lines corresponding to the sense amplifiers, respectively, after the sense amplifiers corresponding to the memory cells latch the data.

Abstract: A primary side current value to be shunted from a DC power source (1) to the primary side of a DC power circuit (2) is detected by a primary side current detection resistor (5), and an output current value to be shunted to an inverter curcuit (3) and its downstream is detected by a current detection resistor (6). On the basis of those current values detected, the total current value to flow into a plurality of load curcuits such as the DC power supply circuit (2) and the inverter circuit (3) is detected by a total current detection unit (7). On the basis of the total current value detected, a control unit (8) controls a switching transistor (24) of the DC power circuit (2) to control an output power thereby to control an electric current (Ib) to be fed from the DC power cource (1).

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: memory cells which need refresh operation; and a refresh control circuit which suspends the refresh operation when external access for reading out from or writing into the memory cells is requested.

Abstract: A discharge lamp ballast apparatus includes a DC/DC converter having a transformer T1 and a DC/DC converter having a transformer T2, which are connected in parallel; a control section 4 for controlling the output voltages of the DC/DC converters by varying their duties with shifting the operation phases of the transformers T1 and T2 of the DC/DC converters; and a voltage-multiplier rectifier circuit having diodes 7-9 and capacitors 10-12 for generating a high voltage used for starting a discharge lamp 22 by utilizing the potential difference between the output voltages of the transformers T1 and T2.

Abstract: A semiconductor storage apparatus according to one embodiment of the present invention, comprising: cell arrays, each having a plurality of memory cells connected to a pair of first and second bit lines; and sense amplifiers, each being provided corresponding to the pair of first and second bit lines and sensing data read out from the memory cell to be read out, wherein each of the sense amplifiers includes a current mirror circuit having first and second current paths connected directly or indirectly to the pair of first and second bit lines; and the current mirror circuit includes: a first transistor which has a source and a drain short-circuited to each other and flows a reference current between the source and the drain; and a second transistor, of which gate is commonly connected to a gate of the first transistor, and which flows a current passing through the memory cell to be read out between a source and a drain thereof.

Abstract: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Abstract: A semiconductor memory device has first and second sense nodes which are provided corresponding to first and second bit lines, and a sense amplifier which is connected to the first and second sense nodes and senses data read out from a memory cell, wherein the sense amplifier includes an initial sense circuit which increases a potential difference between the first and second sense nodes in a first period after beginning sense operation, and a latch circuit which increases and holds the potential difference between the first and second sense nodes in a second period after the first period, wherein the initial sense circuit includes first and second transistors of first conductive type, third and fourth transistors of first conductive type, and fifth and sixth transistors of first conductive type, wherein the latch circuit includes seventh and eighth transistors of first conductive type, and ninth and tenth transistors of second conductive type.

Abstract: This disclosure concerns a memory including a memory cell including a floating body in an electrically floating state and storing data according to the number of majority carriers in the floating body; a word line connected to a gate of the memory cell; a first bit line connected to the memory cell to transmit the data; a second bit line transmitting reference data used to detect the data stored in the memory cell; a first sense node and a second sense node transmitting the data stored in the memory cell and the reference data, respectively; a first short-circuiting switch provided between the first sense node and the second sense node; and a first flip-flop applying a load current to the memory cell during a data read operation and amplifying a potential difference generated between the first sense node and the second sense node by turning off the first short-circuiting switch