Abstract: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The logic gate 70 is connected to the input end of the transfer gate 60. The logic gate 70 serves as a transmission prevention circuit preventing a signal stored in the memory circuit 50 from being transmitted to the fuse 10, when the disconnection judgment takes place.

Abstract: When the state of the vacuum processing chamber is switched to an idle state in which an insulating fluid is circulated while a semiconductor wafer W is not placed in the vacuum processing chamber and no plasma is generated in the vacuum processing chamber, nitrogen gas purging (N2 purging) of the inside of the vacuum processing chamber is started, and the pressure in the vacuum processing chamber is controlled to a predetermined level, for example, about 27 Pa (200 mTorr). This makes it possible to prevent a component in the vacuum processing chamber of a plasma processor from being charged to high voltage, so that an insulative material can be protected against breakdown caused by electric discharge or the like.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.

Abstract: The semiconductor storage device of the present invention is provided with a first cell unit including a first memory cell selection transistor, a first and a second compare transistors and a first capacitor; and a second cell unit including a second memory cell selection transistor, a third and a fourth compare transistors and a second capacitor; the cell units being disposed side by side along a boundary to constitute a memory cell, in which the second compare transistor controlled by a first compare line is connected to a match line, and the fourth compare transistor controlled by a second compare line is connected to a ground line.

Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., −400 to −600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.

Abstract: There is provided a semiconductor device including a semiconductor substrate, a gate electrode formed on the semiconductor substrate, a gate insulating layer sandwiched between the gate electrode and the semiconductor substrate, an interlayer insulating layer formed over the gate electrode and the semiconductor substrate, and a hydroxyl (OH) group trapper formed in the interlayer insulating layer. For instance, the hydroxyl group trapper is constituted of a nitrogen containing oxide layer. The semiconductor device is capable of preventing moisture contained in the interlayer insulating layer from penetrating the gate insulating layer and source/drain regions formed in the semiconductor substrate, resulting in that the semiconductor device can be kept away from being degraded because of hot carriers, even if the gate insulating layer were formed thinner.