Patents by Inventor Takehiro Ueda

Takehiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8871592
    Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8742465
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20140077335
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 20, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Takehiro UEDA
  • Patent number: 8610178
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: December 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20130299083
    Abstract: A substrate mounting table includes a plate shaped member provided with a mounting surface for mounting a substrate thereon, a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface, and a gas supply channel for supplying the gas through the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface. At least inner wall portions of the gas supply channel are formed in curved surface shapes, the inner wall portions facing the gas injection openings.
    Type: Application
    Filed: July 18, 2013
    Publication date: November 14, 2013
    Inventors: Takehiro UEDA, Yoshiyuki KOBAYASHI, Kaoru OOHASHI
  • Patent number: 8573836
    Abstract: An apparatus evaluates a substrate mounting device adapted to hold a target substrate placed on a mounting surface and to control a temperature of the target substrate. The apparatus includes an evacuatable airtightly sealed chamber accommodating therein the substrate mounting device, a heat source, arranged in a facing relationship with the mounting surface, for irradiating infrared light. The apparatus further includes an evaluation-purpose substrate adapted to be mounted on the mounting surface in place of the target substrate, the evaluation-purpose substrate being made of an infrared light absorbing material, and having a unit for measuring temperatures at plural sites on a surface and/or inside of the substrate.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: November 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Yasuharu Sasaki, Takehiro Ueda, Taketoshi Okajo, Kaoru Oohashi
  • Publication number: 20130288445
    Abstract: A method of manufacturing a semiconductor device including a transistor. The method includes forming a channel region by implanting impurity ions of a second conductive type into an element forming region that is formed on one side of a substrate and is partitioned by an element isolation insulating film, forming a trench in said channel region formed on said one side of said substrate, covering side faces and a bottom face of said trench with a gate insulating film by forming said gate insulating film on said one side of said substrate, forming a gate electrode so as to bury an inside of said trench, patterning said gate electrode in a predetermined shape; and forming a source region and a drain region by implanting impurity ions of a first conductive type on both sides of said channel region.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8491752
    Abstract: A substrate mounting table includes a plate shaped member provided with a mounting surface for mounting a substrate thereon, a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface, and a gas supply channel for supplying the gas through the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface. At least inner wall portions of the gas supply channel are formed in curved surface shapes, the inner wall portions facing the gas injection openings.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: July 23, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Takehiro Ueda, Yoshiyuki Kobayashi, Kaoru Oohashi
  • Patent number: 8476701
    Abstract: A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8387562
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: March 5, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Patent number: 8372730
    Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 8362524
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 8299569
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20120267755
    Abstract: A method for cutting an electric fuse formed on a semiconductor substrate by applying a predetermined electric voltage between a first interconnect and a second interconnect to flow an electric current in the electric fuse such that the electric conductor is flowed toward outside from the second interconnect to form a void region between the via and the first interconnects or in the via.
    Type: Application
    Filed: July 3, 2012
    Publication date: October 25, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA
  • Patent number: 8236622
    Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20120006492
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akihiro KIKUCHI, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Publication number: 20110284951
    Abstract: A semiconductor device includes a transistor that has a trench formed in an element forming region of a substrate, a gate insulating film formed on side faces and a bottom face of the trench, a gate electrode formed on the gate insulating film so as to bury the trench, a source region formed on one side in the gate longitude direction, which is formed on the surface of the substrate, and a drain region formed on the other side in the gate longitude direction. Here, the gate electrode is formed so as to be exposed also on the substrate outside the trench, and the gate electrode is disposed so as to cover upper portions of both ends of the trench and so as to form at least one concave portion having a depth reaching the substrate in a center portion.
    Type: Application
    Filed: May 18, 2011
    Publication date: November 24, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Takehiro Ueda, Hiroshi Kawaguchi
  • Patent number: 8056503
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: November 15, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Publication number: 20110267136
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Application
    Filed: July 8, 2011
    Publication date: November 3, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA
  • Publication number: 20110266653
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA