Patents by Inventor Takehiro Ueda

Takehiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190010967
    Abstract: An air cylinder includes a cylinder, a piston rod, a piston, and a controller. The piston rod has one end disposed in the cylinder and the other end protruding from the cylinder. The piston is provided at the one end of the piston rod and moves the piston rod by moving in the cylinder. The controller supplies gas into one of a space, which is a space in the cylinder directed on the piston rod side with respect to the piston, and a space, which is a space in the cylinder opposite to the space with respect to the piston, and sucks gas from an interior of the other of the spaces.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 10, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takehiro UEDA, Takeshi AKAO
  • Publication number: 20190006500
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.
    Type: Application
    Filed: May 22, 2018
    Publication date: January 3, 2019
    Inventors: Takehiro UEDA, Yasuhiro OKAMOTO
  • Patent number: 10135435
    Abstract: A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20180315640
    Abstract: A plasma processing apparatus includes a first mounting table on which a target object to be processed is mounted, a second mounting table provided around the first mounting table, and an elevation mechanism. A focus ring is mounted on the second mounting table. The second mounting table has therein a temperature control mechanism. The elevation mechanism is configured to vertically move the second mounting table.
    Type: Application
    Filed: April 24, 2018
    Publication date: November 1, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takehiro UEDA, Kenji NAGAI
  • Publication number: 20180286948
    Abstract: A high-electron-mobility transistor has a buffer layer, a channel layer, a barrier layer, a mesa-shaped cap layer, a source electrode formed on one side of the cap layer, a drain electrode formed on the other side, and a gate electrode formed over the cap layer via a gate insulating film. The semiconductor device has an element isolation region defining an active region in which the semiconductor device is provided. The gate electrode extends from over the active region to the over the element isolation region. In plan view, the active region has a projection part projected to the direction of the element isolation region in a region overlapped with the gate electrode. By providing the active region with a projection part, the channel length of a parasitic transistor can be increased, and turn-on of the parasitic transistor can be suppressed.
    Type: Application
    Filed: February 6, 2018
    Publication date: October 4, 2018
    Inventor: Takehiro UEDA
  • Publication number: 20180231872
    Abstract: A camera module includes a substrate having a first main surface mounted with an image sensor, a second main surface on the reverse side of the substrate from the first main surface in the predetermined direction, and is provided with at least one hole extending from the first main surface in the predetermined direction. The camera module further includes a holder which has a boss inserted from the first main surface into the at least one hole, and holds at least one lens. The camera module further includes a fixing part made of adhesive that is cured into an anchor shape. The fixing part fixes the boss inside the at least one hole.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: HIROYUKI TAHARA, TAKEHIRO UEDA, KAZUO SIBUKAWA, ATSUKI KAMATANI, YOSHIYUKI HOTTA
  • Publication number: 20180233328
    Abstract: A maintenance apparatus includes a case and a maintenance mechanism. The case includes an opening having a size corresponding to a second gate of a vacuum processing apparatus including a processing chamber having a first gate through which a substrate is loaded and unloaded and the second gate different from the first gate. The case is attachable to the second gate while maintaining airtightness. The maintenance mechanism is provided in the case and is configured to perform at least one of an operation of detaching a consumed part in the processing chamber through the opening, an operation of attaching a replacement part in the processing chamber and an operation of cleaning the processing chamber.
    Type: Application
    Filed: February 15, 2018
    Publication date: August 16, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takehiro UEDA, Jun HIROSE
  • Publication number: 20180190501
    Abstract: Disclosed is a plasma processing apparatus including: a first placing table including a placing surface configured to place thereon a workpiece serving as a plasma processing target, an outer peripheral surface, a heater provided on the placing surface, a power supply terminal provided on a back surface side opposite to the placing table, and a wiring provided on the outer peripheral surface so as to be enclosed in an insulator, the wiring being configured to connect the heater and the power supply terminal; and a second placing table provided along the outer peripheral surface of the first placing table and configured to place a focus ring thereon.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 5, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Takehiro UEDA
  • Publication number: 20180166259
    Abstract: Non-uniformity of temperature of a focus ring can be improved by reducing holes which hamper a heat transfer from the focus ring to a base. A mounting table includes the base configured to place a processing target object thereon; the focus ring provided on the base to surround a region on which the processing target object is placed; a connecting member provided with a through hole and configured to connect the base to a member provided below the base by being inserted into an insertion hole formed at a region of the base which corresponds to a lower portion of the focus ring; and a lifter pin provided at the base such that the lifter pin is allowed to be protruded from the insertion hole by being inserted into the through hole of the connecting member, and configured to raise the focus ring by being protruded from the insertion hole.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 14, 2018
    Inventor: Takehiro Ueda
  • Publication number: 20180159525
    Abstract: A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.
    Type: Application
    Filed: October 30, 2017
    Publication date: June 7, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Takehiro UEDA
  • Patent number: 9728381
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 8, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Patent number: 9620449
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: April 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 9437402
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 6, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Publication number: 20160035673
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Application
    Filed: October 8, 2015
    Publication date: February 4, 2016
    Inventor: Takehiro UEDA
  • Patent number: 9177912
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 3, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 9000559
    Abstract: A semiconductor device includes a semiconductor substrate and an electrical fuse formed on the semiconductor substrate, and including a first conductor and a second conductor electrically separated from the first conductor. In a state of the electrical fuse after a cutting processing, the first conductor is cut and separated into a first part electrically separated from the second conductor and a second part including a flowing region from which a material constituting the first conductor flows outward and which is electrically connected to the second conductor.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20150083332
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akihiro KIKUCHI, Satoshi KAYAMORI, Shinya SHIMA, Yuichiro SAKAMOTO, Kimihiro HIGUCHI, Kaoru OOHASHI, Takehiro UEDA, Munehiro SHIBUYA, Tadashi GONDAI
  • Publication number: 20150083333
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 26, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akihiro KIKUCHI, Satoshi KAYAMORI, Shinya SHIMA, Yuichiro SAKAMOTO, Kimihiro HIGUCHI, Kaoru OOHASHI, Takehiro UEDA, Munehiro SHIBUYA, Tadashi GONDAI
  • Patent number: 8904957
    Abstract: An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., ?400 to ?600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 9, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Satoshi Kayamori, Shinya Shima, Yuichiro Sakamoto, Kimihiro Higuchi, Kaoru Oohashi, Takehiro Ueda, Munehiro Shibuya, Tadashi Gondai
  • Patent number: 8869376
    Abstract: A substrate mounting table includes a plate shaped member provided with a mounting surface for mounting a substrate thereon, a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface, and a gas supply channel for supplying the gas through the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface. At least inner wall portions of the gas supply channel are formed in curved surface shapes, the inner wall portions facing the gas injection openings.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Takehiro Ueda, Yoshiyuki Kobayashi, Kaoru Oohashi