Patents by Inventor Takehiro Ueda

Takehiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110250735
    Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.
    Type: Application
    Filed: June 23, 2011
    Publication date: October 13, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 7998798
    Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7994544
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7989913
    Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7835211
    Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7795699
    Abstract: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: September 14, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20100159673
    Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7728407
    Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: June 1, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7679871
    Abstract: A semiconductor device includes a semiconductor substrate, a fuse which comprises a conductive material and is formed on a semiconductor substrate, a contacting target conductor region which is placed around the fuse on the semiconductor substrate and formed so as to make electrical contact with the fuse through the conductive material constituting the fuse when a process for cutting the fuse is carried out, and a determination unit which detects whether or not the fuse is electrically disconnected, and detects whether or not the contacting target conductor region and the fuse are electrically connected, and determines that the fuse is in a cut state when electrical disconnection of said fuse is detected or electrical connection between said contacting target conductor region and said fuse is detected.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Norio Okada, Takehiro Ueda
  • Publication number: 20100037454
    Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.
    Type: Application
    Filed: October 22, 2009
    Publication date: February 18, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA
  • Patent number: 7646581
    Abstract: An electrostatic chuck capable of widening a temperature range and reducing a variation in thermal conductivity between the electrostatic chuck and the flat substrate over time is provided. The chuck includes: a body that has an internal electrode for attracting a flat substrate by an electrostatic force provided therein, a plurality of protrusions formed on one surface of the body serving as an electrostatic attraction surface, and projections provided on the top surfaces of some or all of the plurality of protrusions. In the electrostatic chuck, a region of the top surface of each of the minute projections on which the flat substrate is loaded is referred to as a mounting surface, and the total area of the mounting surfaces of the minute projections is equal to or larger than 0.01% and equal to or smaller than 2% of the area of the electrostatic attraction surface.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: January 12, 2010
    Assignees: Sumitomo Osaka Cement Co., Ltd., Tokyo Electron Limited
    Inventors: Yasuharu Sasaki, Takehiro Ueda, Yusuke Nakagawa, Nobuyuki Nagayama, Taketoshi Okajo, Mamoru Kosakai
  • Patent number: 7635907
    Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7619264
    Abstract: An electric fuse includes a wide interconnect and a narrow interconnect. The electric fuse has a juxtaposed region in which a plurality of straight line portions are juxtaposed with each other by folding the wide interconnect, and the narrow interconnect has a narrower width than that of the wide interconnect, and, at the same time, is connected to the wide interconnect outside the juxtaposed region.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: November 17, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7592261
    Abstract: When the state of the vacuum processing chamber is switched to an idle state in which an insulating fluid is circulated while a semiconductor wafer W is not placed in the vacuum processing chamber and no plasma is generated in the vacuum processing chamber, nitrogen gas purging (N2 purging) of the inside of the vacuum processing chamber is started, and the pressure in the vacuum processing chamber is controlled to a predetermined level, for example, about 27 Pa (200 mTorr). This makes it possible to prevent a component in the vacuum processing chamber of a plasma processor from being charged to high voltage, so that an insulative material can be protected against breakdown caused by electric discharge or the like.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: September 22, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Takehiro Ueda, Katsuyuki Koizumi, Kouki Suzuki
  • Publication number: 20090174029
    Abstract: A semiconductor device is provided including a first fuse link having a copper-containing metal film, a second fuse link having a polysilicon film, a semiconductor substrate, and a field insulating film formed on the semiconductor substrate. The second fuse link is formed on the field insulating film. An interlayer insulating film is provided between the first fuse link and the second fuse link. The first fuse link is electrically connected to the second fuse link via a first plug formed in the interlayer insulating film.
    Type: Application
    Filed: March 4, 2009
    Publication date: July 9, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20090146251
    Abstract: The semiconductor device of the present invention comprises a semiconductor substrate; and a conductive element formed on the semiconductor substrate and capable of being opened when a predetermined current flows, wherein the conductive element turns plurality of times.
    Type: Application
    Filed: February 10, 2009
    Publication date: June 11, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro UEDA
  • Patent number: 7529147
    Abstract: The semiconductor device has a semiconductor substrate; an electric fuse provided on the semiconductor substrate, and having a first fuse link and a second fuse link connected in series; and a terminal provided between the first fuse link and the second fuse link, wherein the first fuse link and the second fuse link are configured as being different from each other in current value necessary for blowing.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: May 5, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7515497
    Abstract: A fuse peripheral circuit includes a fuse, a potential difference imparting circuit, a potential difference reducing circuit, a terminal, a memory circuit, a transfer gate, and a logic gate. The logic gate is connected to the input end of the transfer gate. The logic gate serves as a transmission prevention circuit preventing a signal stored in the memory circuit from being transmitted to the fuse, when the disconnection judgment takes place.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: April 7, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Patent number: 7489230
    Abstract: A semiconductor device includes a first insulating layer, which is formed on a semiconductor substrate (not shown), and formed with a concave portion, and an electric fuse which has a conductive member, a first terminal provided on one end and a second terminal provided on the other end of the conductive member, and which is provided on the first insulating layer. The first insulating layer is embedded with the conductive member. The conductive member has a flowing-out region in which a material forming the conductive member flows out to the outside of the concave portion, and is cut at a location different from the flowing-out region.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: February 10, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20080212640
    Abstract: A testing apparatus for a temperature monitoring substrate includes a heat flow generating unit for generating a heat flow in the temperature monitoring substrate in a depthwise direction of the temperature sensors, wherein the temperature sensors are buried in the depthwise direction. Further, a testing method for a temperature monitoring substrate includes generating a heat flow in the temperature monitoring substrate in a depthwise direction, wherein the temperature sensors are buried in the depthwise direction; processing a temperature of the substrate measured by the temperature sensor under the heat flow by a prescribed method; and determining whether or not an error occurs in the temperature sensor.
    Type: Application
    Filed: January 25, 2008
    Publication date: September 4, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuharu Sasaki, Takehiro Ueda, Taketoshi Okajo