Patents by Inventor Takehiro Ueda

Takehiro Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7411851
    Abstract: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26, so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36, and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 12, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20080142160
    Abstract: A substrate mounting table includes a plate shaped member provided with a mounting surface for mounting a substrate thereon, a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface, and a gas supply channel for supplying the gas through the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface. At least inner wall portions of the gas supply channel are formed in curved surface shapes, the inner wall portions facing the gas injection openings.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takehiro UEDA, Yoshiyuki Kobayashi, Kaoru Oohashi
  • Publication number: 20080145556
    Abstract: A method for manufacturing a substrate mounting table having a mounting surface for mounting a substrate thereon; a plurality of gas injection openings opened on the mounting surface to supply a gas toward the mounting surface; a gas supply channel for supplying a gas to the gas injection openings; and a thermally sprayed ceramic layer covering the mounting surface is provided. The method includes forming a removable film at least on inner wall portions of the gas supply channel facing the gas injection openings; forming the thermally sprayed ceramic layer on the mounting surface; and removing the film.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 19, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Nobuyuki NAGAYAMA, Takehiro Ueda, Yoshiyuki Kobayashi, Kaoru Oohashi
  • Publication number: 20080122027
    Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.
    Type: Application
    Filed: May 16, 2007
    Publication date: May 29, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 7376036
    Abstract: In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a second test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a second threshold resistance value smaller than the first threshold resistance value.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: May 20, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20080106842
    Abstract: A mounting device includes a mounting body for sustaining a target object to be processed thereon; an electrostatic chuck disposed on the mounting body and having an electrode layer interposed between insulating layers, and the electrostatic chuck serving to electrostatically attract and hold the target object on a surface of the insulating layer by a electrostatic force generated between the electrode layer and the target object by a voltage applied to the electrode layer. Herein, an electrostatic chuck layer, which is one of the insulating layers on the side of a top surface of the electrode layer, is made of a plasma spray coating of yttrium oxide, which is formed by a plasma spraying, having a thickness of about 200 ?m to 280 ?m, and the electrostatic chuck layer has a surface roughness dependent on a particle diameter of the yttrium oxide used in the plasma spraying.
    Type: Application
    Filed: November 2, 2007
    Publication date: May 8, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroharu ITO, Kenichi Kato, Takehiro Ueda
  • Publication number: 20080098833
    Abstract: An apparatus evaluates a substrate mounting device adapted to hold a target substrate placed on a mounting surface and to control a temperature of the target substrate. The apparatus includes an evacuatable airtightly sealed chamber accommodating therein the substrate mounting device, a heat source, arranged in a facing relationship with the mounting surface, for irradiating infrared light. The apparatus further includes an evaluation-purpose substrate adapted to be mounted on the mounting surface in place of the target substrate, the evaluation-purpose substrate being made of an infrared light absorbing material, and having a unit for measuring temperatures at plural sites on a surface and/or inside of the substrate.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 1, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yasuharu Sasaki, Takehiro Ueda, Taketoshi Okajo, Kaoru Oohashi
  • Publication number: 20070278616
    Abstract: A semiconductor device includes a semiconductor substrate and an electrical fuse formed on the semiconductor substrate, and including a first conductor and a second conductor electrically separated from the first conductor. In a state of the electrical fuse after a cutting processing, the first conductor is cut and separated into a first part electrically separated from the second conductor and a second part including a flowing region from which a material constituting the first conductor flows outward and which is electrically connected to the second conductor.
    Type: Application
    Filed: May 23, 2007
    Publication date: December 6, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20070278617
    Abstract: A semiconductor device includes a semiconductor substrate, a fuse which comprises a conductive material and is formed on a semiconductor substrate, a contacting target conductor region which is placed around the fuse on the semiconductor substrate and formed so as to make electrical contact with the fuse through the conductive material constituting the fuse when a process for cutting the fuse is carried out, and a determination unit which detects whether or not the fuse is electrically disconnected, and detects whether or not the contacting target conductor region and the fuse are electrically connected, and determines that the fuse is in a cut state when electrical disconnection of said fuse is detected or electrical connection between said contacting target conductor region and said fuse is detected.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 6, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Norio Okada, Takehiro Ueda
  • Publication number: 20070262414
    Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 15, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20070262357
    Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.
    Type: Application
    Filed: May 11, 2007
    Publication date: November 15, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 7282751
    Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: October 16, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20070222029
    Abstract: A portion to be melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.
    Type: Application
    Filed: May 18, 2007
    Publication date: September 27, 2007
    Applicant: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Publication number: 20070217114
    Abstract: The invention provides an electrostatic chuck capable of widening a temperature range when the temperature of a flat substrate is controlled and reducing a variation in thermal conductivity between the electrostatic chuck and the flat substrate over time. According to an aspect of the invention, an electrostatic chuck includes: a body that has an internal electrode for attracting a flat substrate by an electrostatic force provided therein; a plurality of protrusions that are formed on one surface of the body, serving as an electrostatic attraction surface; and one or more minute projections that are provided on each of top surfaces of some or all of the plurality of protrusions. In the electrostatic chuck, a region of the top surface of each of the minute projections on which the flat substrate is loaded is referred to as a mounting surface, and the total area of the mounting surfaces of the minute projections is equal to or larger than 0.
    Type: Application
    Filed: January 30, 2007
    Publication date: September 20, 2007
    Inventors: Yasuharu Sasaki, Takehiro Ueda, Yusuke Nakagawa, Nobuyuki Nagayama, Taketoshi OKajo, Mamoru Kosakai
  • Publication number: 20070108550
    Abstract: The semiconductor device has a semiconductor substrate; an electric fuse provided on the semiconductor substrate, and having a first fuse link and a second fuse link connected in series; and a terminal provided between the first fuse link and the second fuse link, wherein the first fuse link and the second fuse link are configured as being different from each other in current value necessary for blowing.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 17, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20070052063
    Abstract: An electric fuse includes a wide interconnect and a narrow interconnect. The electric fuse has a juxtaposed region in which a plurality of straight line portions are juxtaposed with each other by folding the wide interconnect and the narrow interconnect has a narrower width than that of the wide interconnect, and, at the same time, is connected to the wide interconnect outside the juxtaposed region.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 8, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20070052515
    Abstract: A semiconductor device includes a first insulating layer, which is formed on a semiconductor substrate (not shown), and formed with a concave portion, and an electric fuse which has a conductive member, a first terminal provided on one end and a second terminal provided on the other end of the conductive member, and which is provided on the first insulating layer. The first insulating layer is embedded with the conductive member. The conductive member has a flowing-out region in which a material forming the conductive member flows out to the outside of the concave portion, and is cut at a location different from the flowing-out region.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 8, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20060200717
    Abstract: In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a second test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a second threshold resistance value smaller than the first threshold resistance value.
    Type: Application
    Filed: February 9, 2006
    Publication date: September 7, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Publication number: 20060171229
    Abstract: A fuse peripheral circuit shown in FIG. 2 has a fuse 10, a potential difference imparting circuit 20, a potential difference reducing circuit 30, a terminal 40, a memory circuit 50, a transfer gate 60, and a logic gate 70. The potential difference imparting circuit 20 is configured as having a transfer gate 22 (first transfer gate), a terminal 24 (first terminal) and a terminal 26, so as to give a predetermined potential difference between both ends of the fuse 10 when disconnection of the fuse 10 is judged. The potential difference reducing circuit 30 is configured as having a transfer gate 32 (second transfer gate), a terminal 34 (second terminal) and a terminal 36, and reduces the potential difference between both ends of the fuse 10 applied by the above-described potential difference imparting circuit 20.
    Type: Application
    Filed: January 18, 2006
    Publication date: August 3, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: D553104
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: October 16, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Kaoru Oohashi, Shunsuke Mizukami, Takehiro Ueda