Abstract: A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j?N2j>N1d and N2j<N2b are satisfied.

Abstract: A silicon carbide semiconductor device has a planar layout configured by periodically arranging unit cells. The unit cells include valid cells and invalid cells. Each of the valid cells has a switchable channel surface. The invalid cells are to relax electric field in the valid cells. At least one of the valid cells is disposed between adjacent ones of the invalid cells.

Abstract: A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.

Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom.

Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than ?3° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm?3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.

Abstract: A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.

Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than ?40 ?m and not greater than ?5 ?m, and a value for warp at the main surface being not smaller than 5 ?m and not greater than 40 ?m. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

Abstract: A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.

Abstract: A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.

Abstract: A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1?ND/NA?50 is satisfied is within 1 ?m therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract: A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.

Abstract: A method for manufacturing a SiC semiconductor device includes: a step of forming an oxide film on a surface of a SiC substrate; and a step of removing the oxide film. In the step of forming the oxide film, ozone gas is used. In the step of removing the oxide film, it is preferable to use halogen plasma or hydrogen plasma. In this way, problems associated with a chemical solution can be reduced while obtaining a method and device for manufacturing a SiC semiconductor device, by each of which a cleaning effect can be improved.

Abstract: A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.

Abstract: A method for manufacturing a MOSFET includes the steps of: introducing an impurity into a silicon carbide layer; forming a carbon layer in a surface layer portion of the silicon carbide layer having the impurity introduced therein, by selectively removing silicon from the surface layer portion; and activating the impurity by heating the silicon carbide layer having the carbon layer formed therein.

Abstract: A method for manufacturing a MOSFET includes the steps of: forming a gate oxide film on an active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode in ohmic contact with the active layer, and forming an interlayer insulating film made of silicon dioxide so as to cover the gate electrode after the source contact electrode is formed. The step of forming a source contact electrode includes the steps of forming a metal layer including aluminum so as to be in contact with the active layer, and alloying the metal layer.

Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.

Abstract: A gate electrode includes a polysilicon film in contact with a gate insulating film, a barrier film provided on the polysilicon film, a metal film provided on the barrier film and made of refractory metal. An interlayer insulating film is arranged so as to cover the gate insulating film and the gate electrode provided on the gate insulating film. The interlayer insulating film has a substrate contact hole partially exposing a silicon carbide substrate in a region in contact with the gate insulating film. A interconnection is electrically connected to the silicon carbide substrate through the substrate contact hole and is electrically insulated from the gate electrode by the interlayer insulating film.