Patents by Inventor Takeyoshi Masuda

Takeyoshi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120315746
    Abstract: An impurity of a first conductivity type is implanted onto a silicon carbide substrate through an opening in a mask layer. First and second films made of first and second materials respectively are formed. It is sensed that etching of the first material is performed during anisotropic etching, and then anisotropic etching is stopped. An impurity of a second conductivity type is implanted onto the silicon carbide substrate through the opening narrowed by the first and second films. Thus, the impurity regions can be formed in an accurately self-aligned manner.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsuke YAMADA, Takeyoshi MASUDA
  • Publication number: 20120313112
    Abstract: A MOSFET includes a silicon carbide substrate, a drift layer made of silicon carbide and including a main surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, and a gate oxide film formed on and in contact with the main surface of the drift layer. The drift layer includes a p type body region formed to include a region in contact with the gate oxide film. The p type body region has an impurity density of 5×1016 cm?3 or more. A plurality of p type regions of p conductivity type located apart from one another in a direction perpendicular to a thickness direction of the drift layer are arranged in a region in the drift layer lying between the p type body region and the silicon carbide substrate.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 13, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Misako Honaga, Toru Hiyoshi
  • Publication number: 20120305943
    Abstract: A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j?N2j>N1d and N2j<N2b are satisfied.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Misako HONAGA, Takeyoshi MASUDA, Keiji WADA, Toru HIYOSHI
  • Publication number: 20120309195
    Abstract: A method for manufacturing a high-quality semiconductor device having stable characteristics is provided. The method for manufacturing the semiconductor device includes the steps of: preparing a silicon carbide layer having a main surface; forming a trench in the main surface by removing a portion of the silicon carbide layer; and removing a portion of a side wall of the trench by thermal etching.
    Type: Application
    Filed: July 29, 2011
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takeyoshi Masuda
  • Publication number: 20120309174
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a silicon carbide substrate, forming an active layer on the silicon carbide substrate, forming a gate oxide film on the active layer, forming a gate electrode on the gate oxide film, forming a source contact electrode on the active layer, and forming a source interconnection on the source contact electrode. The step of forming the source interconnection includes the steps of forming a conductor film on the source contact electrode and processing the conductor film by etching the conductor film with reactive ion etching. Then, the method of manufacturing a MOSFET further includes the step of performing annealing of heating the silicon carbide substrate to a temperature not lower than 50° C. after the step of processing the conductor film.
    Type: Application
    Filed: December 7, 2011
    Publication date: December 6, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda
  • Publication number: 20120292742
    Abstract: A MOSFET includes a silicon carbide substrate, a buffer layer made of silicon carbide formed on the silicon carbide substrate, a drift layer made of silicon carbide of an n conductivity type formed on the buffer layer, a p type body region of a p conductivity type formed in the drift layer to include a main surface of the drift layer opposite to the buffer layer, a source contact electrode formed on the p type body region, and a drain electrode formed on a main surface of the silicon carbide substrate opposite to the buffer layer. A current path region having an impurity concentration higher than that of another region in the drift layer is formed in a region in the drift layer sandwiched between the buffer layer and the body region.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 22, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Satomi Itoh, Takeyoshi Masuda
  • Publication number: 20120286291
    Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.
    Type: Application
    Filed: March 4, 2011
    Publication date: November 15, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Publication number: 20120280255
    Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.
    Type: Application
    Filed: October 25, 2011
    Publication date: November 8, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi
  • Patent number: 8283674
    Abstract: MOSFET is provided with SiC film. SiC film has a facet on its surface, and the length of one period of the facet is 100 nm or more, and the facet is used as channel. Further, a manufacturing method of MOSFET includes: a step of forming SiC film; a heat treatment step of heat-treating SiC film in a state where Si is supplied on the surface of SiC film; and a step of forming the facet obtained on the surface of SiC film by the heat treatment step into a channel. Thereby, it is possible to sufficiently improve the characteristics.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: October 9, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Shinji Matsukawa
  • Publication number: 20120248462
    Abstract: An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm?3 or more.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Misako Honaga, Toru Hiyoshi
  • Publication number: 20120248461
    Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Toru Hiyoshi, Keiji Wada
  • Publication number: 20120235165
    Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than ?° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm?3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.
    Type: Application
    Filed: December 17, 2010
    Publication date: September 20, 2012
    Applicant: Sumitomo Electric Industries, Ltd
    Inventors: Shin Harada, Toru ` Hiyoshi, Keiji Wada, Takeyoshi Masuda
  • Publication number: 20120231618
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takeyoshi MASUDA
  • Publication number: 20120231617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom.
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takeyoshi MASUDA
  • Publication number: 20120228640
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.
    Type: Application
    Filed: July 14, 2011
    Publication date: September 13, 2012
    Applicant: Sumitomo Electric Industries Ltd
    Inventors: Takeyoshi Masuda, Shin Harada, Misako Honaga, Keiji Wada, Toru Hiyoshi
  • Publication number: 20120208368
    Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
    Type: Application
    Filed: February 25, 2011
    Publication date: August 16, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Satomi Itoh, Toru Hiyoshi
  • Publication number: 20120193643
    Abstract: A MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a p type body region in which an inversion layer is formed when the gate electrode is fed with a voltage. The inversion layer has an electron mobility ? dependent more strongly on an acceptor concentration Na of a channel region of the p type body region, as compared with a dependency of the electron mobility ? being proportional to the reciprocal of the acceptor concentration Na. The acceptor concentration Na in the channel region of the p type body region is not less than 1×1016 cm?3 and not more than 2×1018 cm3. The channel length (L) is equal to or smaller than 0.43 ?m. The channel length (L) is equal to or longer than a spreading width d of a depletion layer in the channel region. The spreading width d is expressed by d=D·Na?C.
    Type: Application
    Filed: February 1, 2012
    Publication date: August 2, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi MASUDA, Toru Hiyoshi, Keiji Wada
  • Publication number: 20120190137
    Abstract: Provided is a cross section observation method, including the steps of: forming a marker layer at a base material, the marker layer having a conductivity different from that of another portion of the base material; forming a sample, by performing treatment on the base material at which the marker layer is formed; and detecting secondary electrons generated by emitting electrons to a cross section of the sample.
    Type: Application
    Filed: January 24, 2011
    Publication date: July 26, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Satomi ITO, Takeyoshi MASUDA
  • Publication number: 20120168774
    Abstract: A silicon carbide substrate and a method for manufacturing the silicon carbide substrate are obtained, each of which achieves reduced manufacturing cost of semiconductor devices using the silicon carbide substrate. A method for manufacturing a SiC-combined substrate includes the steps of: preparing a plurality of single-crystal bodies each made of silicon carbide (SiC); forming a collected body; connecting the single-crystal bodies to each other; and slicing the collected body. In the step, the plurality of SiC single-crystal ingots are arranged with a silicon (Si) containing Si layer interposed therebetween, so as to form the collected body including the single-crystal bodies. In the step, adjacent SiC single-crystal ingots are connected to each other via at least a portion of the Si layer, the portion being formed into silicon carbide by heating the collected body. In step, the collected body in which the SiC single-crystal ingots are connected to each other is sliced.
    Type: Application
    Filed: May 19, 2011
    Publication date: July 5, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Satomi Itoh, Shin Harada, Makoto Sasaki
  • Publication number: 20120171850
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip.
    Type: Application
    Filed: August 24, 2010
    Publication date: July 5, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Misako Honaga, Takeyoshi Masuda, Shin Harada