Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first and second plane, first and second trench extending in first direction, and in the silicon carbide layer, n-type first region, p-type second region between the n-type first region and the first plane and between the first and second trench, p-type fifth region covering bottom of the first trench, p-type sixth region covering bottom of the second trench, n-type seventh region between the fifth region and the second region, n-type eighth region between the sixth and second regions, p-type ninth regions contacting the fifth and second regions, and p-type tenth regions contacting the sixth region and the second region, the ninth and tenth regions repeatedly disposed in the first direction, and a line segment connecting the ninth region and the tenth region is oblique with respect to second direction perpendicular to the first direction.

Abstract: A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.

Abstract: According to one embodiment, a semiconductor device includes a first layer, a first electrode, and a first nitride region. The first layer includes a first material and a first partial region. The first material includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The first partial region is of a first conductivity type. The first conductivity type is one of an n-type or a p-type. A direction from the first partial region toward the first electrode is aligned with a first direction. The first nitride region includes Alx1/Ga1-x1/N (0?x1<1), is provided between the first partial region and the first electrode, is of the first conductivity type, and includes a first protrusion protruding in the first direction.

Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).

Abstract: An embodiment is a semiconductor device includes a silicon carbide layer having a first plane and a second plane facing the first plane; a gate electrode; an aluminum nitride layer located between the silicon carbide layer and the gate electrode, the aluminum nitride layer containing an aluminum nitride crystal; a first insulating layer located between the silicon carbide layer and the aluminum nitride layer; and a second insulating layer located between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: An embodiment of a semiconductor device including a silicon carbide layer having a first and a second planes; a first silicon carbide region of first conductivity type in the silicon carbide layer; a second silicon carbide region of second conductivity type in the silicon carbide layer between the first silicon carbide region and the first plane; a third silicon carbide region of the first conductivity type in the silicon carbide layer located between the second silicon carbide region and the first plane; a first electrode located on a side of the first plane; a second electrode located on a side of the second plane; a gate electrode; an aluminum nitride layer containing an aluminum nitride crystal between the second silicon carbide region and the gate electrode; and an insulating layer between the aluminum nitride layer and the gate electrode and having a wider band gap than the aluminum nitride layer.

Abstract: A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm?3 and not higher than 5×1022 cm?3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and a first crystal member. A direction from the first electrode toward the second electrode is aligned with a first direction. A position in the first direction of the third electrode is between positions in the first direction of the first electrode and the second electrode. The semiconductor member includes at least one selected from the group consisting of silicon carbide, silicon, carbon, and germanium. The semiconductor member includes a first region, and first and second partial regions. The first region is between the first and second electrodes in the first direction. A second direction from the first region toward the third electrode crosses the first direction. The first crystal member is provided between the first and third electrodes in the second direction.

Abstract: A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.

Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.

Abstract: A semiconductor device includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (SiO2)n (Si3N4)m (wherein n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer provided between the silicon carbide layer and the gate electrode; and a region located between the silicon carbide layer and the gate insulating layer, the region having a first bonding structure, the first bonding structure including a threefold coordinated first nitrogen atom bonded to three first silicon atoms, a threefold coordinated second nitrogen atom bonded to three second silicon atoms, and a threefold coordinated third nitrogen atom bonded to three third silicon atoms, the first to third nitrogen atoms being adjacent to each other in the first bonding structure.

Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; a first n-type silicon carbide region disposed in the silicon carbide layer; and a first nitrogen region disposed in the silicon carbide layer, the first nitrogen region disposed between the first n-type silicon carbide region and the first electrode, and the first nitrogen region having a first nitrogen concentration higher than a first n-type impurity concentration of the first n-type silicon carbide region.

Abstract: According to one embodiment, a semiconductor device includes a first element. The first element includes a first electrode, a second electrode and first to fourth semiconductor regions. The second electrode includes a first conductive region and a second conductive region. The first semiconductor region is provided between the first electrode and the first conductive region and between the first electrode and the second conductive region. The second semiconductor region includes a first partial region and a second partial region. The first partial region is provided between the first electrode and the first conductive region. The second partial region is provided between the first electrode and the second conductive region. The third semiconductor region is provided between the second partial region and the second conductive region. The fourth semiconductor region is provided between the third semiconductor region and the second conductive region.

Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.

Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.

Abstract: The present invention provides a lathe that is provided with an eccentricity adjustment mechanism that makes it possible for electrical components that are readily affected by the environment to be eliminated from the turntable; for slip rings in particular, which exhibit problems in terms of the durability of signal transmission during high-speed rotation, to be eliminated as well, and for safe and stable adjustment of workpiece eccentricity to be easily achieved. A lathe provided with an eccentricity adjustment mechanism, in which a linear motion guide unit (6) is provided in an inclined state in an engaging part of the center part of a turntable (1) and an axial-direction-movement part (5A) of a center shaft (5); and, due to the center shaft (5) being moved, the turntable (1) moves in the radial direction by the radial pressing force generated by the linear motion guide unit (6) being inclined, and the eccentricity of the workpiece (3) is adjusted.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer provided between the silicon carbide layer and the gate electrode; and a region located between the silicon carbide layer and the gate insulating layer, the region having a first bonding structure, the first bonding structure including a threefold coordinated first nitrogen atom bonded to three first silicon atoms, a threefold coordinated second nitrogen atom bonded to three second silicon atoms, and a threefold coordinated third nitrogen atom bonded to three third silicon atoms, the first to third nitrogen atoms being adjacent to each other in the first bonding structure.

Abstract: A diamond substrate according to an embodiment includes a diamond layer including at least one first element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), the number of threefold coordinated atoms of the at least one first element in the diamond layer being larger than the number of fourfold coordinated atoms of the at least one first element in the diamond layer, a surface of the diamond layer having an off angle of 10 degrees or less with respect to a (111) face.