Patents by Inventor Tatsuo Shimizu

Tatsuo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10229994
    Abstract: A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Publication number: 20190067423
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face, a silicon oxide layer, and a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.
    Type: Application
    Filed: February 9, 2018
    Publication date: February 28, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke IIJIMA
  • Patent number: 10217811
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face, a silicon oxide layer, and a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: February 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10211301
    Abstract: A semiconductor device according to an embodiment includes: a wide bandgap semiconductor layer; a gate electrode; and a gate insulating layer disposed between the wide bandgap semiconductor layer and the gate electrode, including a first silicon oxide film, a second silicon oxide film between the first silicon oxide film and the gate electrode, and a first aluminum oxynitride film between the first silicon oxide film and the second silicon oxide film, and having a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the first aluminum oxynitride film which is lower than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position, closer to the second silicon oxide film than the first position, in the first aluminum oxynitride film.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: February 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10186596
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer, a gate electrode, and a silicon oxide layer disposed between the silicon carbide layer and the gate electrode, a number of single bonds between carbon atoms being larger than that of double bonds between carbon atoms in the silicon oxide layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: January 22, 2019
    Assignees: Kabushiki Kaisha Toshiba, National Institute for Materials Science
    Inventors: Tatsuo Shimizu, Takahisa Ohno, Tomoaki Kaneko, Takahiro Yamasaki, Nobuo Tajima, Jun Nara
  • Patent number: 10177009
    Abstract: A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 10177251
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: January 8, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takashi Shinohe, Ryosuke Iijima
  • Publication number: 20180374918
    Abstract: A semiconductor device of the embodiment includes: a first region provided in a silicon carbide layer; and a second region provided around the first region in the silicon carbide layer, the second region having a higher concentration of at least one kind of a lifetime killer impurity selected from the group consisting of B (boron), Ti (titanium), V (vanadium), He (helium) and H+ (proton) than a concentration of a lifetime killer impurity in the first region.
    Type: Application
    Filed: February 7, 2018
    Publication date: December 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Johji NISHIO, Mitsuhiro Kushibe, Tatsuo Shimizu
  • Patent number: 10153347
    Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito, Hiroshi Ono
  • Patent number: 10141410
    Abstract: A semiconductor device according to an embodiment includes an n-type SiC region, an electrode in contact with the SiC region, and a region including oxygen, the region provided in the SiC region, the region being provided on an electrode side of the SiC region.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Publication number: 20180337275
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: November 22, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Takashi SHINOHE, Ryosuke llJIMA
  • Publication number: 20180308936
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a gate electrode; an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode; a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region; a third silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), positioned between the first electrode and the second silicon carbide region and spaced apart from the first silicon carbide region; and a gate insulating layer positioned between the gate electrode and the second silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Masayasu MIYATA, Hirotaka NISHINO, Yoshihiko MORIYAMA, Yuichiro MITANI
  • Publication number: 20180308950
    Abstract: A semiconductor device includes a nitride semiconductor layer, a first electrode and second electrode on the nitride semiconductor layer, a gate electrode, and a gate insulating layer between the nitride semiconductor layer and the gate electrode. The gate insulating layer has a first oxide region containing at least any one element of aluminum and boron, gallium, and silicon. When a distance between the first end portion and the second end portion of the first oxide region is defined as d1, and a position separated by d1/10 from the first end portion toward the second end portion is defined as a first position, an atomic concentration of gallium at the first position is 80% or more and 120% or less of that of the at least any one element.
    Type: Application
    Filed: February 6, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Hisashi SAITO, Hiroshi ONO, Toshiya YONEHARA
  • Publication number: 20180308935
    Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.
    Type: Application
    Filed: February 8, 2018
    Publication date: October 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Publication number: 20180304379
    Abstract: The present invention provides a lathe that is provided with an eccentricity adjustment mechanism that makes it possible for electrical components that are readily affected by the environment to be eliminated from the turntable; for slip rings in particular, which exhibit problems in terms of the durability of signal transmission during high-speed rotation, to be eliminated as well, and for safe and stable adjustment of workpiece eccentricity to be easily achieved. A lathe provided with an eccentricity adjustment mechanism, in which a linear motion guide unit (6) is provided in an inclined state in an engaging part of the center part of a turntable (1) and an axial-direction-movement part (5A) of a center shaft (5); and, due to the center shaft (5) being moved, the turntable (1) moves in the radial direction by the radial pressing force generated by the linear motion guide unit (6) being inclined, and the eccentricity of the workpiece (3) is adjusted.
    Type: Application
    Filed: October 7, 2016
    Publication date: October 25, 2018
    Applicant: O-M LTD.
    Inventors: Tatsuo SHIMIZU, Takio NAKAMURA, Hirofumi NAKAKUBO, Akira NISHIYAMA
  • Patent number: 10103231
    Abstract: According to one embodiment, a semiconductor device includes a first element portion. The first element portion includes first and second semiconductor layers, first, second and third electrodes, and a first insulating layer. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first electrode is separated from the first semiconductor layer. The first electrode includes a polycrystal of a nitride of one of Al or B. The second semiconductor layer includes Alx2Ga1-x2N (x1<x2<1). The second semiconductor layer includes first to third regions. The first region is positioned between the second and third regions. The first region is provided between the first semiconductor layer and the first electrode. The first insulating layer is provided between the first region and the first electrode. The second electrode is electrically connected to the second region. The third electrode is electrically connected to the third region.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 16, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koyama, Hisashi Saito, Tatsuo Shimizu, Shinya Nunoue
  • Publication number: 20180286953
    Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke llJIMA
  • Publication number: 20180277643
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer, an insulating layer, and a region provided between the silicon carbide layer and the insulating layer, the region including a plurality of first atoms of one element from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), at least some of the plurality of first atoms being four-fold coordinated atoms and/or five-fold coordinated atoms.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke llJIMA
  • Publication number: 20180269290
    Abstract: A nitride semiconductor device includes a first semiconductor layer including a nitride semiconductor, a second semiconductor layer contacting the first semiconductor layer and including a nitride semiconductor, a source electrode, a drain electrode, a first gate electrode, a second gate electrode provided on an opposite side, a first insulating layer and a second insulating layer. The gate electrode has a protrusion portion inside the semiconductor layer. A distance between the first gate electrode and the protrusion portion of the second gate electrode is shorter than a distance between the source electrode and the second insulating layer, and shorter than a distance between the drain electrode and the second insulating layer.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 20, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Aya SHINDOME, Hisashi SAITO, Tatsuo SHIMIZU
  • Patent number: 10079285
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region and the insulating layer in the nitride semiconductor layer and has a higher electric resistivity than the first region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 18, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito