Patents by Inventor Tatsuo Shimizu

Tatsuo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267457
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Publication number: 20190259620
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming an insulating layer having a first plane in contact with a nitride semiconductor layer and a second plane opposite to the first plane and containing at least one of an oxide and an oxynitride; and performing first heat treatment at 600° C. or more and 1100° C. or less in a state where a voltage making a first plane side positive relative to a second plane side is applied to the insulating layer.
    Type: Application
    Filed: August 20, 2018
    Publication date: August 22, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yasutaka Nishida, Toshiya Yonehara
  • Patent number: 10388742
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, an insulating layer provided on the nitride semiconductor layer, a first region provided in the nitride semiconductor layer, and a second region which is provided between the first region in the nitride semiconductor layer and the insulating layer, has a higher electric resistivity than the first region, and includes carbon (C).
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 20, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10381491
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; an n-type silicon carbide region disposed in the silicon carbide layer and having a first nitrogen concentration; a first p-type silicon carbide region disposed in the silicon carbide layer between the n-type silicon carbide region and the first electrode and having a second nitrogen concentration higher than the first nitrogen concentration; and a second p-type silicon carbide region disposed in the silicon carbide layer between the first p-type silicon carbide region and the first electrode, having a third nitrogen concentration higher than the second nitrogen concentration, and having a p-type impurity concentration higher than that of the first p-type silicon carbide region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 13, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Publication number: 20190244812
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including a first compound including silicon and carbon, and a second semiconductor region including a second compound including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first region and the second region. The first region and the second region include germanium. The third region does not include germanium, or a concentration of germanium in the third region is lower than a concentration of germanium in the first region and lower than a concentration of germanium in the second region.
    Type: Application
    Filed: August 6, 2018
    Publication date: August 8, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji NISHIO, Tatsuo SHIMIZU, Mitsuhiro KUSHIBE
  • Publication number: 20190245042
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including first and second compounds including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first and second regions. The first and second regions include a first element. The first element includes at least one selected from the group consisting of second and third elements. The second element includes at least one selected from the group consisting of Ar, Kr, Xe, and Rn. The third element includes at least one selected from the group consisting of Cl, Br, I, and At. The third region does not include the first element, or a concentration of the first element in the third region is lower than concentrations of the first element in the first and second regions.
    Type: Application
    Filed: August 6, 2018
    Publication date: August 8, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji NISHIO, Tatsuo Shimizu, Mitsuhiro Kushibe
  • Patent number: 10347734
    Abstract: A semiconductor device includes a nitride semiconductor layer, a first electrode and second electrode on the nitride semiconductor layer, a gate electrode, and a gate insulating layer between the nitride semiconductor layer and the gate electrode. The gate insulating layer has a first oxide region containing at least any one element of aluminum and boron, gallium, and silicon. When a distance between the first end portion and the second end portion of the first oxide region is defined as d1, and a position separated by d1/10 from the first end portion toward the second end portion is defined as a first position, an atomic concentration of gallium at the first position is 80% or more and 120% or less of that of the at least any one element.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito, Hiroshi Ono, Toshiya Yonehara
  • Publication number: 20190198634
    Abstract: A semiconductor device includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (SiO2)n (Si3N4)m (wherein n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 27, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Hisashi Saito
  • Publication number: 20190189758
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Toshiya YONEHARA, Hiroshi ONO, Daimotsu KATO, Akira MUKAI
  • Patent number: 10319819
    Abstract: A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC semiconductor layer and the gate electrode, and a region that is provided between the SiC semiconductor layer and the gate insulating film and includes at least one element selected from the group consisting of antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The concentration of the at least one element is equal to or greater than 1×1019 cm?3 and equal to or less than 2.4×1022 cm?3.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: June 11, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuo Shimizu, Takashi Shinohe
  • Patent number: 10319828
    Abstract: A semiconductor device according to an embodiment includes a semiconductor region, a gate electrode, and a first gate insulating film provided between the semiconductor region and the gate electrode and containing a material having a chemical composition expressed by (SiO2)n(Si3N4)m (where n and m are positive integers), in the material, at least one silicon atom being bonded with at least one oxygen atom and at least one nitrogen atom.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 11, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito
  • Publication number: 20190144262
    Abstract: Provided is microparticle extraction technology capable of stably extracting only a target microparticle at high speed from a sheath flow flowing through a flow path. A particle extraction apparatus includes: a first extraction unit for extracting, from a whole sample containing a target particle, an extraction sample containing the target particle without performing abort processing; and a second extraction unit for subjecting the extraction sample to abort processing and extracting only the target particle.
    Type: Application
    Filed: February 22, 2017
    Publication date: May 16, 2019
    Applicant: Sony Corporation
    Inventors: Tatsuo Shimizu, Kazuya Takahashi, Yu Hirono
  • Patent number: 10290731
    Abstract: A semiconductor device of an embodiment includes a nitride semiconductor layer, a first electrode provided on the nitride semiconductor layer, a second electrode provided on the nitride semiconductor layer, a third electrode provided above the nitride semiconductor layer, the third electrode provided between the first electrode and the second electrode, the third electrode containing a polycrystalline nitride semiconductor containing a p-type impurity, and a first insulating layer provided between the nitride semiconductor layer and the third electrode.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Tatsuo Shimizu
  • Publication number: 20190115461
    Abstract: In one embodiment, a semiconductor device is provided with a semiconductor layer made of a nitride semiconductor, a first gate electrode, a first structure body between the first gate electrode and the semiconductor layer, and a first insulating layer between the semiconductor layer and the first structure body. The first structure body has a first intermediate layer made of a conductor to suppress generation of charges at respective interfaces with adjacent layers, a first layer having dielectric property between the first gate electrode and the first intermediate layer, and a second layer having dielectric property between the first gate electrode and the first layer, and has dipoles at an interface between the first layer and the second layer.
    Type: Application
    Filed: August 31, 2018
    Publication date: April 18, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Tatsuo Shimizu, Hiroshi Ono, Daimotsu Kato
  • Patent number: 10256308
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 10249718
    Abstract: A semiconductor device according to an embodiment includes a metal layer; an n-type first silicon carbide region; and a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt) and positioned between the metal layer and the first silicon carbide region.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masayasu Miyata, Hirotaka Nishino, Yoshihiko Moriyama, Yuichiro Mitani
  • Patent number: 10243058
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including a nitride semiconductor, a first electrode separated from the first semiconductor layer in a first direction, and a first insulating film including silicon and oxygen and being provided between the first semiconductor layer and the first electrode. The first insulating film has a first thickness in the first direction. The first insulating film includes a first position, and a distance between the first position and the first semiconductor layer is ½ of the first thickness. A first hydrogen concentration of hydrogen at the first position is 2.5×1019 atoms/cm3 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Hisashi Saito, Yosuke Kajiwara, Daimotsu Kato, Tatsuo Shimizu, Yasutaka Nishida
  • Patent number: 10243049
    Abstract: A nitride semiconductor device includes a first semiconductor layer including a nitride semiconductor, a second semiconductor layer contacting the first semiconductor layer and including a nitride semiconductor, a source electrode, a drain electrode, a first gate electrode, a second gate electrode provided on an opposite side, a first insulating layer and a second insulating layer. The gate electrode has a protrusion portion inside the semiconductor layer. A distance between the first gate electrode and the protrusion portion of the second gate electrode is shorter than a distance between the source electrode and the second insulating layer, and shorter than a distance between the drain electrode and the second insulating layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aya Shindome, Hisashi Saito, Tatsuo Shimizu
  • Patent number: 10236341
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Tatsuo Shimizu
  • Patent number: 10236353
    Abstract: A semiconductor device of an embodiment includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap than the first nitride semiconductor layer, a first electrode on the second nitride semiconductor layer, a second electrode on the second nitride semiconductor layer, a gate electrode located between the first electrode and the second electrode, and a first insulating layer located at least between the gate electrode and the second electrode on the second nitride semiconductor layer, the first insulating layer being an oxide of at least one first element selected from the group consisting of Hf, Zr, and Ti, and containing 5×1019 cm?3 or more of at least one second element selected from the group consisting of F, H, D, V, Nb, and Ta, and 5×1019 cm?3 or more of at least one third element selected from the group consisting of N, P, As, Sb, Bi, Be, Mg, Ca, Sr, Ba, Sc, Y, and lanthanoids.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tatsuo Shimizu