Patents by Inventor Tatsuo Shimizu

Tatsuo Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10580874
    Abstract: A semiconductor device according to the embodiments described herein includes a silicon carbide layer and a silicon oxide layer. The silicon oxide layer is disposed on the silicon carbide layer and contains at least one element selected from a group of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). In the silicon oxide layer, at least a part of the at least one element is single bonded to three oxygen atoms and double bonded to one oxygen atom.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 3, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10573735
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and an intermediate region. A position of the first electrode is between a position of the second electrode and a position of the third electrode. The first semiconductor region is separated from the first, second, and third electrodes. The second semiconductor region is provided between the second electrode and the first semiconductor region. The third semiconductor region is provided between the third electrode and the first semiconductor region. The intermediate region includes at least one of a first compound or a second compound. At least a portion of the first electrode is positioned between the second and third semiconductor regions. The intermediate region includes a first partial region, a second partial region, and a third partial region.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 25, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Koyama, Tatsuo Shimizu, Shinya Nunoue
  • Patent number: 10566451
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Akira Mukai
  • Publication number: 20200035791
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having a first and second plane, first and second trench extending in first direction, and in the silicon carbide layer, n-type first region, p-type second region between the n-type first region and the first plane and between the first and second trench, p-type fifth region covering bottom of the first trench, p-type sixth region covering bottom of the second trench, n-type seventh region between the fifth region and the second region, n-type eighth region between the sixth and second regions, p-type ninth regions contacting the fifth and second regions, and p-type tenth regions contacting the sixth region and the second region, the ninth and tenth regions repeatedly disposed in the first direction, and a line segment connecting the ninth region and the tenth region is oblique with respect to second direction perpendicular to the first direction.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 30, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki OSHIMA, Shinya Kyogoku, Ryosuke Iijima, Tatsuo Shimizu
  • Patent number: 10546932
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including first and second compounds including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first and second regions. The first and second regions include a first element. The first element includes at least one selected from the group consisting of second and third elements. The second element includes at least one selected from the group consisting of Ar, Kr, Xe, and Rn. The third element includes at least one selected from the group consisting of Cl, Br, I, and At. The third region does not include the first element, or a concentration of the first element in the third region is lower than concentrations of the first element in the first and second regions.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 28, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji Nishio, Tatsuo Shimizu, Mitsuhiro Kushibe
  • Patent number: 10546931
    Abstract: A semiconductor device according to embodiments described herein includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes a first layer, a second layer, a first region, and a second region. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is provided across the first layer and the second layer, includes a first element from F, D, and H, and has a first concentration peak of the first element. The second region is provided in the first layer, includes a second element from Ge, B, Al, Ga, In, Be, Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid, and has a second concentration peak of the second element and a third concentration peak of C.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: January 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima
  • Patent number: 10541307
    Abstract: A semiconductor device according to an embodiment includes a p-type SiC layer and a contact electrode electrically connected to the SiC layer. The contact electrode includes metal. And a region is provided in the SiC layer adjacent to the contact electrode. The region having an oxygen concentration not lower than 1×1016 cm?3 and not higher than 1×1021 cm?3.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10535744
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer on the first nitride semiconductor layer; a first electrode and a second electrode disposed on or above the first nitride semiconductor layer; a gate electrode above the first nitride semiconductor layer; and a gate insulating layer, the gate insulating layer including a silicon oxide film and an aluminum oxynitride film, the aluminum oxynitride film disposed between the first nitride semiconductor layer and the silicon oxide film, a first atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a first position in the aluminum oxynitride film being higher than a second atomic ratio of nitrogen relative to a sum of oxygen and nitrogen at a second position in the aluminum oxynitride film, and the second position being closer to the silicon oxide film than the first position.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: January 14, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Toshiya Yonehara, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 10529558
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including a first compound including silicon and carbon, and a second semiconductor region including a second compound including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first region and the second region. The first region and the second region include germanium. The third region does not include germanium, or a concentration of germanium in the third region is lower than a concentration of germanium in the first region and lower than a concentration of germanium in the second region.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Johji Nishio, Tatsuo Shimizu, Mitsuhiro Kushibe
  • Publication number: 20190386127
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.
    Type: Application
    Filed: March 11, 2019
    Publication date: December 19, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daimotsu KATO, Toshiya Yonehara, Hiroshi Ono, Yosuke Kajiwara, Masahiko Kuraguchi, Tatsuo Shimizu
  • Patent number: 10497572
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes: forming an insulating layer having a first plane in contact with a nitride semiconductor layer and a second plane opposite to the first plane and containing at least one of an oxide and an oxynitride; and performing first heat treatment at 600° C. or more and 1100° C. or less in a state where a voltage making a first plane side positive relative to a second plane side is applied to the insulating layer.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yasutaka Nishida, Toshiya Yonehara
  • Publication number: 20190363161
    Abstract: A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm?3 and not higher than 5×1022 cm?3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke IIJIMA, Johji NISHIO, Teruyuki OHASHI
  • Patent number: 10431657
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor regions, first to third electrodes, a conductive portion, first and second insulating layers. The first, second and third electrodes are separated from the first semiconductor region. The conductive portion is separated from the first semiconductor region. The second semiconductor region includes first to third partial regions. The first and second partial regions are electrically connected to the first and second electrodes, respectively. The third partial region is positioned between the second portion and the first semiconductor region. A portion of the first insulating layer is provided between the first portion and the first semiconductor region. The second insulating layer includes first and second insulating portions. The first insulating portion is positioned between the second portion and the third partial region.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: October 1, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya Shindome, Masahiko Kuraguchi, Tatsuo Shimizu
  • Publication number: 20190296146
    Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).
    Type: Application
    Filed: August 27, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Ryosuke IIJIMA, Toshihide ITO, Shunsuke ASABA, Yukio NAKABAYASHI, Shigeto FUKATSU
  • Publication number: 20190296156
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; a first n-type silicon carbide region disposed in the silicon carbide layer; and a first nitrogen region disposed in the silicon carbide layer, the first nitrogen region disposed between the first n-type silicon carbide region and the first electrode, and the first nitrogen region having a first nitrogen concentration higher than a first n-type impurity concentration of the first n-type silicon carbide region.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo SHIMIZU
  • Patent number: 10424640
    Abstract: A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm?3 and not higher than 5×1022 cm?3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 24, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Ryosuke Iijima, Johji Nishio, Teruyuki Ohashi
  • Publication number: 20190288081
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor regions, first to third electrodes, a conductive portion, first and second insulating layers. The first, second and third electrodes are separated from the first semiconductor region. The conductive portion is separated from the first semiconductor region. The second semiconductor region includes first to third partial regions. The first and second partial regions are electrically connected to the first and second electrodes, respectively. The third partial region is positioned between the second portion and the first semiconductor region. A portion of the first insulating layer is provided between the first portion and the first semiconductor region. The second insulating layer includes first and second insulating portions. The first insulating portion is positioned between the second portion and the third partial region.
    Type: Application
    Filed: August 7, 2018
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Aya SHINDOME, Masahiko KURAGUCHI, Tatsuo SHIMIZU
  • Publication number: 20190280112
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer; an insulating layer; a first region disposed between the nitride semiconductor layer and the insulating layer and containing at least one element of hydrogen and deuterium; and a second region disposed in the nitride semiconductor layer, adjacent to the first region, and containing fluorine.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Masahiko Kuraguchi, Toshiya Yonehara, Akira Mukai
  • Publication number: 20190280111
    Abstract: A semiconductor device according to an embodiment includes a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer, a first and second electrode located on or above the first nitride semiconductor layer; a trench located in the second nitride semiconductor layer between the first electrode and the second electrode, and including a bottom surface and a side surface, the bottom surface being located in one of the first nitride semiconductor layer and the second nitride semiconductor layer; a gate electrode located in the trench; a gate insulating layer located between the bottom surface and the gate electrode and between the side surface and the gate electrode; and a region located in at least one of the first nitride semiconductor layer and the second nitride semiconductor layer, including a first portion adjacent to the bottom surface, and containing fluorine.
    Type: Application
    Filed: August 24, 2018
    Publication date: September 12, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo SHIMIZU, Toshiya YONEHARA, Akira MUKAI
  • Publication number: 20190273135
    Abstract: According to one embodiment, a semiconductor device includes a first element. The first element includes a first electrode, a second electrode and first to fourth semiconductor regions. The second electrode includes a first conductive region and a second conductive region. The first semiconductor region is provided between the first electrode and the first conductive region and between the first electrode and the second conductive region. The second semiconductor region includes a first partial region and a second partial region. The first partial region is provided between the first electrode and the first conductive region. The second partial region is provided between the first electrode and the second conductive region. The third semiconductor region is provided between the second partial region and the second conductive region. The fourth semiconductor region is provided between the third semiconductor region and the second conductive region.
    Type: Application
    Filed: August 10, 2018
    Publication date: September 5, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chiharu Ota, Tatsunori Sakano, Tatsuo Shimizu, Ryosuke Iijima