Patents by Inventor Taylor R. Efland

Taylor R. Efland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5306652
    Abstract: A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12) . A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).
    Type: Grant
    Filed: December 30, 1991
    Date of Patent: April 26, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Oh-Kyong Kwon, Taylor R. Efland, Satwinder Malhi, Wai T. Ng
  • Patent number: 5182222
    Abstract: A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer.
    Type: Grant
    Filed: June 26, 1991
    Date of Patent: January 26, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Satwinder Malhi, Taylor R. Efland
  • Patent number: 5119162
    Abstract: Methods and circuits of integrated DMOS, CMOS, NPN, and PNP devices include self-aligned DMOS (411) with increased breakdown voltage and ruggedness for recovery from transients including additional Zener diodes (402/474).
    Type: Grant
    Filed: December 19, 1989
    Date of Patent: June 2, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: James R. Todd, David R. Cotton, Taylor R. Efland, John K. Lee, Roy C. Jones, III