Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Abstract: A locking structure and a buckling washer are provided. The locking structure is provided for locking an object having a thru-hole. The locking structure includes a stud sleeve, a buckling washer, and a screw. The buckling washer is disposed on the stud sleeve, and the buckling washer includes a carrying portion and a plurality of hook portions. The carrying portion has a penetrating hole, and the hook portions extend from the carrying portion and are arranged outside of the penetrating hole. The carrying portion of the buckling washer is configured to carry the object, and the hook portions are configured to retain the object. The screw is configured to be screwed in the stud sleeve by passing through the thru-hole of the object and the penetrating hole of the buckling washer, such that the object is locked by the hook portions.

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: This disclosure is related to an ultraviolet fluid sterilizing box structure. A box (10) includes a chamber (100), a water inlet (101) and a water outlet (102). The water inlet (101) and the water outlet (102) are located on different sides of the box (10). The partition (20) is disposed in the chamber (100) and includes an outer cylinder (21) and an inner cylinder (22). The outer cylinder (21) includes an outer cavity (210) and an inflow inlet (211). The inner cylinder (22) includes an inner cavity (220) and an opening (221). The ultraviolet module (30) is disposed on one side of the box (10) and includes a light-transmitting plate (31) and an ultraviolet lamp set (32). The light-transmitting plate (31) seals the outer cylinder (21). The ultraviolet rays irradiate the inner cavity (220) and the outer cavity (210).

Abstract: A memory cell array is provided. The memory cell array includes: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines electrically connected to the plurality of rows, respectively; a plurality of source lines electrically connected to the plurality of columns, respectively; and a plurality of bit lines electrically connected to the plurality of columns, respectively. A plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

Abstract: A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.

Abstract: In some embodiments, the present disclosure relates to a 3D memory device, including a plurality of gate lines interleaved between a plurality of dielectric layers in a vertical direction, the plurality of gate lines forming recesses between the plurality of dielectric layers; a source/drain line disposed next to the plurality of dielectric layers, spaced from the plurality of gate lines by the recesses in a lateral direction; a ferroelectric film arranged laterally between sidewalls of the plurality of gate lines and the source/drain line and confined within the recesses; and a semiconductor film disposed within the recesses and spacing the ferroelectric film from the source/drain line.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: A method includes forming a gate structure across a channel region from a top view, the gate structure comprising a work function metal and a gate dielectric layer wrapping around the work function metal, the gate dielectric layer having a U-shaped cross-sectional profile; performing a first plasma etching process, by using a chlorine-containing reactant, on the gate structure; performing a second plasma etching process, by using a bromine-containing, reactant on the gate structure.

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

Abstract: A spiral water filling device including a fixing base, a rotating shaft tube, a motor, a carrier frame, a reciprocating screw, a transmission gear set, a nut slider, and a water filling pipe. The rotating shaft tube is pivotally disposed on the fixing base. The motor engages with the rotating shaft tube. The carrier frame is connected with the rotating shaft tube and has a first guiding structure. The reciprocating screw is perpendicular to the rotating shaft tube and parallel to the first guiding structure. The reciprocating screw and the rotating shaft tube are non-intersected. The transmission gear set is connected between the rotating shaft tube and the reciprocating screw. The nut slider engages with the reciprocating screw. The nut slider has a water outlet and a second guiding structure. The water filling pipe passes through the rotating shaft tube and connects with the water outlet.

Abstract: A method of manufacturing a memory cell includes the following steps. A channel material is formed to contact a source line and a bit line. A ferroelectric (FE) material is formed to contact the channel material. A word line is formed to contact the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

Abstract: A positioning fixture including a shielding member and a driving member is provided. The shielding member includes a sliding part slidably connected to a functional module, a guiding part, and a shielding part. The sliding part and the shielding part respectively extend from two opposite ends of the guiding part. The driving member is movably disposed on the functional module corresponding to the shielding member. The driving member includes a base part, a driving part that contacts the guiding part, and a pillar part, which protrudes from the base part and is adapted to pass through the guiding groove. When the functional module is positioned on the circuit board, the base part of the driving member is pushed by the electronic component, and the guiding part is pushed by the driving part, so that the shielding member slides and the shielding part shields a screw hole of the circuit board.

Abstract: A method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process. The lateral etching process includes a radical etching process and a chemical etching process. Alternatively, the lateral etching process includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.

Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.