Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, an interfacial layer, and a gate electrode. The source region and the drain region are respectively disposed on two opposite ends of the insulating layer. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The interfacial layer is sandwiched between the channel layer and the ferroelectric layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: A memory array includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: A first thin film transistor and a second thin film transistor include a semiconducting metal oxide plate located over a substrate, and a set of electrode structures located on the semiconducting metal oxide plate and comprising, from one side to another, a first source electrode, a first gate electrode, a drain electrode, a second gate electrode, and a second source electrode. A bit line is electrically connected to the drain electrode, and laterally extends along a horizontal direction. A first capacitor structure includes a first conductive node that is electrically connected to the first source electrode. A second capacitor structure includes a second conductive node that is electrically connected to the second source electrode.

Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.

Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.

Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.

Abstract: An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.

Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.