Patents by Inventor Te-An Lin

Te-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Inner spacer formation in multi-gate transistors
    Patent number: 11830928
    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Semiconductor device with air-spacer
    Patent number: 11830922
    Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen
  • Embedded ferroelectric FinFET memory device
    Patent number: 11832450
    Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
  • MULTI-GATE SELECTOR SWITCHES FOR MEMORY CELLS AND METHODS OF FORMING THE SAME
    Publication number: 20230380186
    Abstract: A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Yong-Jie WU, Yen-Chung HO, Hui-Hsien WEI, Chia-Jung YU, Pin-Cheng HSU, Mauricio MANFRINI, Chung-Te LIN
  • FERROELECTRIC MEMORY DEVICES HAVING IMPROVED FERROELECTRIC PROPERTIES AND METHODS OF MAKING THE SAME
    Publication number: 20230378354
    Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Po-Ting LIN, Song-Fu LIAO, Rainer Yen-Chieh HUANG, Hai-Ching CHEN, Yu-Ming LIN, Chung-Te LIN
  • COCKTAIL LAYER OVER GATE DIELECTRIC LAYER OF FET FERAM
    Publication number: 20230380177
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 23, 2023
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • MEMORY ARRAY TEST METHOD AND SYSTEM
    Publication number: 20230377670
    Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: Chien-Hao HUANG, Katherine H. CHIANG, Cheng-Yi WU, Chung-Te LIN
  • THIN FILM TRANSISTOR INCLUDING A COMPOSITIONALLY-MODULATED ACTIVE REGION AND METHODS FOR FORMING THE SAME
    Publication number: 20230378369
    Abstract: A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 23, 2023
    Inventors: Wu-Wei TSAI, Po-Ting LIN, Hai-Ching CHEN, Chung-Te LIN
  • MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF
    Publication number: 20230380182
    Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Hui-Hsien WEI, Chung-Te LIN, Han-Ting TSAI, Tai-Yen PENG, Yu-Teng DAI, Chien-Min LEE, Sheng-Chih LAI, Wei-Chih WEN
  • Memory Array Staircase Structure
    Publication number: 20230377624
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • High-loading ratchet tool
    Patent number: 11819982
    Abstract: Disclosed is a high-loading ratchet tool, which has a main body, a braking structure and a working part, wherein the main body forms a first receiving groove, a second receiving groove and a third receiving groove, and the second receiving groove and the third receiving groove are mainly composed of two circular surfaces, and the braking structure is disposed on the main body. The braking structure has a ratchet, and the two ends of the ratchet respectively form a first shaft segment and a second shaft segment. The first shaft segment is disposed in the second receiving groove, and the second shaft segment is disposed in the third receiving groove. According to this, the relative force of the first shaft segment and the second shaft segment and the main body is dispersed, and enhancing the working part restrictions on external torsion.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 21, 2023
    Inventor: Tsung-Te Lin
  • CAVITY IN METAL INTERCONNECT STRUCTURE
    Publication number: 20230369107
    Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Li-Shyue Lai, Gao-Ming Wu, Katherine H. Chiang, Chung-Te Lin
  • PATTERN FIDELITY ENHANCEMENT
    Publication number: 20230369047
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.
    Type: Application
    Filed: July 30, 2023
    Publication date: November 16, 2023
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
  • PERIPHERAL CIRCUITRY UNDER ARRAY MEMORY DEVICE AND METHOD OF FABRICATING THEREOF
    Publication number: 20230371261
    Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • STACKED FERROELECTRIC STRUCTURE
    Publication number: 20230371272
    Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Rainer Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20230371259
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a first access line extending in a horizontal direction, a first column of memory cells over the first access line, a second column of memory cells adjacent to the first column of memory cells, and a second access line over the first column of memory cells and the second column of memory cells and extending in the horizontal direction. The first column of memory cells includes a first gate line electrically connected to the first access line, and the second column of memory cells includes a second gate line electrically connected to the second access line.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih LAI, Chung-Te LIN
  • INSULATED-GATE BIPOLAR TRANSISTOR (IGBT) DEVICE WITH 3D ISOLATION
    Publication number: 20230369475
    Abstract: An insulated gate bipolar transistor (IGBT) includes: a semiconductor substrate having a top surface extending in a horizontal plane; a three-dimensional (3D) isolation region comprising a silicon compound, the 3D isolation region having a bottom portion and a sidewall portion; a collector region of a first conductive type disposed on the 3D isolation region; a buffer region of a second conductive type opposite to the first conductive type disposed on the collector region; a drift region of the second conductive type disposed on the buffer region; a body region of the first conductive type disposed in the drift region; and at least one source region of the second conductive type disposed in the body region. The 3D isolation region and the top surface of the semiconductor substrate enclose the collector region, the buffer region, the drift region, the body region, and the at least one source region.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Inventor: Hung-Te Lin
  • SEMICONDUCTOR DEVICES
    Publication number: 20230371273
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • TRI-GATE ORTHOGONAL CHANNEL TRANSISTOR AND METHODS OF FORMING THE SAME
    Publication number: 20230369429
    Abstract: A semiconductor device includes a metal oxide semiconductor channel layer, a first gate dielectric layer contacting a first portion of a major surface of the metal oxide semiconductor channel layer, a first gate electrode overlying the first gate dielectric layer and contacting a second portion of the major surface of the metal oxide semiconductor channel layer, a drain region and a backside gate dielectric layer contacting another major surface of the metal oxide semiconductor channel layer, a backside gate electrode contacting the backside gate dielectric layer, a second gate dielectric layer contacting an end surface of the metal oxide semiconductor channel layer, a second gate electrode contacting a surface of the second gate dielectric layer, and a source region contacting another end surface of the metal oxide semiconductor channel layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Katherine H. CHIANG, Chung-Te LIN
  • IN-SITU THERMAL ANNEALING OF ELECTRODE TO FORM SEED LAYER FOR IMPROVING FERAM PERFORMANCE
    Publication number: 20230369420
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Yen-Chieh Huang, Po-Ting Lin, Song-Fu Liao, Hai-Ching Chen, Chung-Te Lin