Patents by Inventor Te-An Lin

Te-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and manufacturing method thereof
    Patent number: 11856869
    Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
  • Three-dimensional memory device and method
    Patent number: 11856782
    Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Ling, Katherine H. Chiang, Chung-Te Lin
  • MRAM device structures and method of fabricating the same
    Patent number: 11856854
    Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes receiving a workpiece including a magnetic tunneling junction (MTJ) and a conductive capping layer disposed on the MTJ, depositing a first dielectric layer over the workpiece, performing a first planarization process to the first dielectric layer, and after the performing of the first planarization process, patterning the first dielectric layer to form an opening exposing a top surface of the conductive capping layer, selectively removing the conductive capping layer. The method also includes depositing an electrode layer to fill the opening and performing a second planarization process to the workpiece such that a top surface of the electrode layer and a top surface of the first dielectric layer are coplanar.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Yin, Min-Kun Dai, Chien-Hua Huang, Chung-Te Lin
  • DOUBLE GATE FERROELECTRIC FIELD EFFECT TRANSISTOR DEVICES AND METHODS FOR FORMING THE SAME
    Publication number: 20230411522
    Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 21, 2023
    Inventors: Yen-Chieh HUANG, Song-Fu LIAO, Po-Ting LIN, Hai-Ching CHEN, Sai-Hooi YEONG, Yu-Ming LIN, Chung-Te LIN
  • INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF
    Publication number: 20230413514
    Abstract: An integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate and includes a first dielectric layer and a memory module. The memory module includes a first memory device, a second memory device, and a third memory device. The first memory device is embedded in the first dielectric layer. The second memory device is disposed aside the first memory device and is embedded in the first dielectric layer. The first memory device, the second memory device, and the third memory device are different types of memory devices.
    Type: Application
    Filed: June 19, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Katherine H CHIANG, Chung-Te Lin
  • Method of fabricating magneto-resistive random access memory (MRAM)
    Patent number: 11849644
    Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chang-Lin Yang, Chung-Te Lin, Sheng-Yuan Chang, Han-Ting Lin, Chien-Hua Huang
  • Semiconductor device and manufacturing method thereof
    Patent number: 11848332
    Abstract: A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gao-Ming Wu, Katherine H. Chiang, Chien-Hao Huang, Chung-Te Lin
  • SELECTIVE ETCHING METHOD AND SEMICONDUCTOR STRUCTURE MANUFACTURED USING THE SAME
    Publication number: 20230402287
    Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Da HUANG, Chun-Fu KUO, Yi-Hsing YU, Li-Te LIN
  • EMBEDDED FERROELECTRIC FINFET MEMORY DEVICE
    Publication number: 20230403860
    Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
    Type: Application
    Filed: August 3, 2023
    Publication date: December 14, 2023
    Inventors: Bo-Feng Young, Chung-Te Lin, Sai-Hooi Yeong, Yu-Ming Lin, Sheng-Chih Lai, Chih-Yu Chang, Han-Jong Chia
  • Semiconductor structure and manufacturing method thereof
    Patent number: 11843056
    Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
  • Resin composition and article made therefrom
    Patent number: 11840630
    Abstract: A resin composition includes 50 parts by weight of a vinyl-containing polyphenylene ether resin, 1 part by weight to 30 parts by weight of a styrene-butadiene-styrene block copolymer and 0.5 part by weight to 30 parts by weight of a zinc molybdate-covered silica, wherein the zinc molybdate-covered silica has a mass ratio of zinc molybdate to silica of between 1:9 and 2:8. The resin composition may be used to make various articles, such as a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including gel time stability, copper foil peeling strength, difference rate of dissipation factor and conductive anodic filament test.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: December 12, 2023
    Assignee: ELITE MATERIAL CO., LTD.
    Inventors: Yu-Te Lin, Chien-Cheng Wang
  • Gate etch back with reduced loading effect
    Patent number: 11843041
    Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • INTEGRATED CIRCUIT, TRANSISTOR AND MEHTOD OF FABRICATING THE SAME
    Publication number: 20230395673
    Abstract: A transistor includes a gate electrode, a gate dielectric, a channel layer and a source line and bit line. The gate electrode includes a first gate material layer and a second gate material layer disposed on the first gate material layer, wherein a work function of the first gate material layer is lower than a work function of the second gate material layer. The gate dielectric is disposed on the gate electrode. The channel layer is disposed on the gate dielectric. The source line and bit line are disposed on and connected to the channel layer.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Cheng Chu, Tzu-Hsiang Hsu, Pin-Cheng Hsu, Chung-Te Lin
  • MEMORY CELL, MEMORY ARRAY AND MANUFACTURING METHOD THEREOF
    Publication number: 20230397426
    Abstract: A 3D memory array including multiple memory cells and a method of manufacturing the same are provided. Each memory cell includes a first isolation structure, source and drain electrodes, a gate layer, a channel layer and a memory layer. The source and drain electrodes are disposed on opposite sides of the first isolation structure, and the source and drain electrodes comprise kink portions. The gate layer is disposed beside the source and drain electrodes and the first isolation structure. The channel layer is disposed between the gate layer and the source electrode, the first isolation structure and the drain electrode, and the channel layer extends between the source and drain electrodes and covers the kink portions of the source and drain electrodes. The memory layer is disposed between the gate layer and the channel layer and extends beside the gate layer and extends beyond the channel layer.
    Type: Application
    Filed: June 5, 2022
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, TsuChing Yang, Sheng-Chih Lai, Feng-Cheng Yang, Chung-Te Lin
  • Transistors with enhanced dopant profile and methods for forming the same
    Patent number: 11837667
    Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20230386921
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • SEMICONDUCTOR DEVICE
    Publication number: 20230387108
    Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Te LIN, Wei-Yuan LU, Feng-Cheng YANG
  • THREE-DIMENSIONAL MEMORY DEVICE AND METHOD
    Publication number: 20230389326
    Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Yu Ling, Katherine H. Chiang, Chung-Te Lin
  • MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230389320
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
  • Semiconductor Device with Air-Spacer
    Publication number: 20230387247
    Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventors: Wei-Yang Lee, Feng-Cheng Yang, Chung-Te Lin, Yen-Ming Chen