Abstract: A semiconductor device includes a first semiconductor region that has an external profile including at least one corner, and that includes a semiconductor of a first conductivity type, and a first insulation region that surrounds an outer periphery of the first semiconductor region, and that includes an insulator that, at a corner portion corresponding to the corner, has a depth deeper than a depth at a location other than the corner portion. The semiconductor device further includes a second semiconductor region that surrounds an outer periphery of the first insulation region, and that includes a semiconductor of a second conductivity type, and a second insulation region that surrounds an outer periphery of the second semiconductor region, and that includes an insulator that is deeper than the depth of the first insulation region at the location other than the corner portion.

Abstract: To provide a voltage regulator capable of maintaining the accuracy of an output voltage even if it is set to an arbitrary output voltage. A voltage regulator includes an output transistor comprised of an NMOS transistor having a backgate grounded, an error amplifier circuit configured to amplify and output a difference between a divided voltage obtained by dividing an output voltage outputted from the output transistor and a reference voltage and thereby to control a gate of the output transistor, a constant voltage circuit, and a transistor having a gate inputted with a voltage of the constant voltage circuit, a drain connected to the gate of the output transistor, and a source connected to a source of the output transistor.

Abstract: Provided is a voltage regulator including a leakage current sink circuit capable of suppressing an influence of a leakage current of an output transistor at high temperature, and reducing power consumption of the voltage regulator at normal temperature. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current sink circuit connected to an output terminal and configured to be prevented from operating at normal temperature, and suppress an influence of a leakage current from the output transistor only at high temperature.

Abstract: Provided is a voltage regulator including a leakage current correction circuit capable of keeping the accuracy of an output voltage of the voltage regulator even when an output voltage of a reference voltage circuit is decreased due to the influence of a leakage current. The voltage regulator includes: a reference voltage circuit configured to output a reference voltage; an output transistor configured to output an output voltage; a voltage divider circuit configured to divide the output voltage to output a feedback voltage; an error amplifier circuit configured to amplify a difference between the reference voltage and the feedback voltage, and output the amplified difference to control a gate of the output transistor; and a leakage current correction circuit connected to an output terminal of the voltage divider circuit. The leakage current correction circuit is configured to decrease the feedback voltage to prevent the output voltage from dropping at high temperature.

Abstract: A voltage regulator having good transient response characteristics and maintaining stable operation is provided. The voltage regulator includes: a first MOS transistor having a gate terminal connected to an output terminal of the differential amplifier circuit; a first constant current source provided between the first MOS transistor and a ground terminal; an output MOS transistor having a gate terminal connected to a drain terminal of the first MOS transistor via a phase compensation circuit; a second MOS transistor having a gate terminal to which an output of the differential amplifier circuit is input and a drain terminal connected to the gate terminal of the output MOS transistor; and a second constant current source provided between the second MOS transistor and a ground terminal.

Abstract: An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: Provided is a voltage regulator capable of setting an accurate short-circuit current. Used as a circuit for determining a current value of a short-circuit current of an overcurrent protection circuit is not a resistor for converting current into voltage but a circuit for controlling in the form of current, that is, a circuit of an N-channel depletion type transistor including a gate and a drain that are connected to each other and operating in a non-saturated state. The N-channel depletion type transistor has process fluctuations that are linked with those of a detection transistor, and hence an accurate short-circuit current may be set without trimming.

Abstract: A voltage regulator having good transient response characteristics and maintaining stable operation is provided. The voltage regulator includes: a first MOS transistor having a gate terminal connected to an output terminal of the differential amplifier circuit; a first constant current source provided between the first MOS transistor and a ground terminal; an output MOS transistor having a gate terminal connected to a drain terminal of the first MOS transistor via a phase compensation circuit; a second MOS transistor having a gate terminal to which an output of the differential amplifier circuit is input and a drain terminal connected to the gate terminal of the output MOS transistor; and a second constant current source provided between the second MOS transistor and a ground terminal.

Abstract: Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode MOS transistor and a first enhancement mode MOS transistor. The soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground.

Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.

Abstract: A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.

Abstract: Provided is a reference voltage circuit having a soft start function, which is small in circuit size and is capable of providing a continuous voltage. The reference voltage circuit includes a reference voltage section and a soft start circuit. The reference voltage section includes a depletion mode MOS transistor and a first enhancement mode MOS transistor. The soft start circuit includes: a second enhancement mode MOS transistor having a gate connected to a gate and a drain of the first enhancement mode MOS transistor, and a drain connected to an output terminal of the reference voltage circuit; a MOS switch having one terminal connected to an output terminal of the reference voltage section, and another terminal connected to the drain of the second enhancement mode MOS transistor; and a constant current source and a capacitor connected in series between a power supply and a ground.

Abstract: Provided is a voltage regulator capable of setting an accurate short-circuit current. Used as a circuit for determining a current value of a short-circuit current of an overcurrent protection circuit is not a resistor for converting current into voltage but a circuit for controlling in the form of current, that is, a circuit of an N-channel depletion type transistor including a gate and a drain that are connected to each other and operating in a non-saturated state. The N-channel depletion type transistor has process fluctuations that are linked with those of a detection transistor, and hence an accurate short-circuit current may be set without trimming.

Abstract: Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor (21) is in an off state during loading and writing and is in an on state during reading. An NMOS transistor (22) is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor (23) is in the off state during loading and writing and is in the on state during reading. A PMOS transistor (26) is in the on state during loading and is in the off state during writing and reading. A PMOS transistor (27) is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.

Abstract: A power supply clamp circuit includes a first transistor including a metal silicide layer that is formed in a substrate between a first electrode coupling part in a first drain region and a first gate electrode, and a second transistor including a first metal silicide layer and a second metal silicide layer each of which is formed in a substrate between a second electrode coupling part in a second drain region and a second gate electrode, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other.

Abstract: Provided is a voltage regulator for limiting a rush current from an output stage transistor. The voltage regulator includes an output current limiting circuit having a low detection current value and an output current limiting circuit having a high detection current value, and is structured so as to enable operation of the output current limiting circuit having a low detection current value during a time period from a state in which an overheat protection circuit detects overheat and an output current is stopped to a state in which an overheat protection is canceled and a predetermined time passes. Accordingly, after the overheat protection is cancelled, an excessive rush current can be limited.

Abstract: A voltage regulator has an output transistor that receives an input voltage inputted via an input terminal and that outputs a constant output voltage via an output terminal. A voltage divider circuit divides the output voltage to generate a divided voltage. A reference voltage circuit generates a reference voltage. An error amplifier circuit generates an error signal by comparing the divided voltage with the reference voltage. A protection circuit detects an abnormal state of the voltage regulator. A control circuit controls the output transistor to increase the output voltage to maintain the output voltage constant when an error signal is generated by the error amplifier circuit, and does not control the output transistor to increase the output voltage when the protection circuit detects an abnormal state of the voltage regulator.

Abstract: The I/O circuit 1 is provided with a first NMOS driver 10 having a drain connected to a pad, a second NMOS driver 11 arranged in an active area which differs from the first NMOS driver 10 and having a drain connected to a source of the first NMOS driver 10 and a source connected to a ground potential, a level converter converting a level of an internal power source potential to a level of a power source potential, and a first NMOS transistor 26 having a drain connected to one output terminal of the level converter, a source connected to a ground potential, and a gate connected to another output of the level converter, and wherein the drain of the first NMOS transistor is connected to the gate of the second NMOS 11.

Abstract: Provided is a voltage regulator capable of reducing fluctuation of an output current even when an output terminal thereof is short-circuited. In a case where the output terminal of the voltage regulator is short-circuited, an output current (Iout) of the voltage regulator is limited and fixed to a limit current value. When an output voltage (Vout) of the voltage regulator decreases to have a value equal to or smaller than not a detection voltage value (Vref3) of a reference voltage circuit (34) but a detection voltage value (Vref2) of a reference voltage circuit (31), a second limit operation in which the output voltage (Iout) is further limited to be decreased is set. Further, in a case where the output terminal is short-circuited and then reset, when the output voltage (Vout) has a value equal to or larger than not the detection voltage value (Vref2) but the detection voltage value (Vref3), the second limit operation is canceled.