Abstract: Provided is a voltage regulator for limiting a rush current from an output stage transistor. The voltage regulator includes an output current limiting circuit having a low detection current value and an output current limiting circuit having a high detection current value, and is structured so as to enable operation of the output current limiting circuit having a low detection current value during a time period from a state in which an overheat protection circuit detects overheat and an output current is stopped to a state in which an overheat protection is canceled and a predetermined time passes. Accordingly, after the overheat protection is cancelled, an excessive rush current can be limited.

Abstract: Provided is a voltage regulator in which a rush current of an output circuit can be limited and a rise time of an output voltage is short. The voltage regulator includes a first output current limiting circuit and a second output current limiting circuit which are used to control the output circuit, and a detecting circuit for detecting a rise speed of an input voltage. The operation of the first output current limiting circuit whose detection current value is low is controlled by the detecting circuit.

Abstract: To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

Abstract: Provided is a DC-DC converter including a short-circuit protection circuit which can stably perform a reset operation and a stop operation. The short-circuit protection circuit includes a detection circuit, a delay circuit, and a latch circuit. The delay circuit is reset in response to an output voltage abnormality signal related to a switching regulator which is outputted from the latch circuit. The latch circuit is reset based on an AND operation between the output voltage abnormality signal and a UVLO signal.

Abstract: To enhance a safety of a voltage regulator, provided is a control circuit (22), which controls the PMOS (1) to be turned on and operates so as to increase the output voltage (VOUT) when the output voltage (VOUT) drops transiently due to rapid fluctuations of a load (RL) connected to an output terminal and the predetermined conditions are not satisfied, and does not perform an operation for increasing the output voltage (VOUT) and causes the protection circuit (50) to protect the voltage regulator when the output voltage (VOUT) drops transiently and the predetermined conditions are satisfied.

Abstract: An electrostatic discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first suicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode.

Abstract: Provided is a voltage regulator in which a rush current of an output circuit can be limited and a rise time of an output voltage is short. The voltage regulator includes a first output current limiting circuit and a second output current limiting circuit which are used to control the output circuit, and a detecting circuit for detecting a rise speed of an input voltage. The operation of the first output current limiting circuit whose detection current value is low is controlled by the detecting circuit.

Abstract: A voltage regulator has an output transistor connected between a power supply and an output terminal, and a voltage amplifying circuit that compares a feedback voltage with a reference voltage to control the output transistor. A transient response improving circuit has a detecting portion that detects fluctuations in the power supply voltage and controls the operating current of the voltage amplifying circuit based on the detected fluctuation level of the power supply voltage thereby improving the responsiveness and reducing power consumption of the voltage regulator.

Abstract: Provided is a DC-DC converter including a short-circuit protection circuit which can stably perform a reset operation and a stop operation. The short-circuit protection circuit includes a detection circuit, a delay circuit, and a latch circuit. The delay circuit is reset in response to an output voltage abnormality signal related to a switching regulator which is outputted from the latch circuit. The latch circuit is reset based on an AND operation between the output voltage abnormality signal and a UVLO signal.

Abstract: To present a semiconductor device mounting ESD protective device appropriately applicable to transistors mutually different in dielectric strength, and its manufacturing method. The semiconductor device comprises a first ESD protective circuit 1A including a first transistor 3 and a first ballast resistance 4, and a second ESD protective circuit 1B including a second transistor 5 and a second ballast resistance 6. The impurity concentration of the second diffusion region forming the first ballast resistance 4 is set lower than the impurity concentration of the fourth diffusion region for forming the second ballast resistance 6.

Abstract: A power clamp circuit for preventing unnecessary power supply leak current at a tolerable power supply noise level. A reference voltage circuit generates a reference voltage by reducing a positive voltage supplied from a first power supply terminal by a predetermined potential and supplies the reference voltage to a buffer circuit. The buffer circuit activates a transistor functioning as a clamp element based on the reference voltage to short-circuit the first and second power supply terminals.

Abstract: To provide a voltage regulator which is excellent in responsibility with low power consumption. A transient response improving circuit of a voltage regulator is provided with a detection portion for detecting a power supply voltage. An operating current of a voltage amplifying circuit is controlled by detecting a fluctuation level in a power supply voltage. As a result, the voltage regulator is provided which is excellent in responsibility with low power consumption.

Abstract: A protection transistor which protects an internal transistor in an internal circuit from breakage due to static electricity occurring between power supply pads is provided. A conductivity type of a first p-well constructing a channel of the protection transistor corresponds to a conductivity type of a second p-well constructing a channel of the internal transistor. An impurity concentration of the first p-well is higher than an impurity concentration of the second p-well. Accordingly, drain junction of the protection transistor is sharper than drain junction of the internal transistor, and starting voltage of a parasitic bipolar operation of the protection transistor is lower than that of the internal transistor. Therefore, the internal circuit can be properly protected from an ESD surge.

Abstract: An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

Abstract: A cleaning method for cleaning a developer container includes a step of blowing air through an opening formed in the developer container at a first flow rate; a step of sucking air through the opening at a second flow rate which is larger than the first flow rate; wherein while the blowing and suction steps are being simultaneously carried out, ambient air is permitted to enter the developer container through an ambient air inlet.

Abstract: An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

Abstract: A cleaning method for cleaning a developer container includes a step of blowing air through an opening formed in the developer container at a first flow rate; a step of sucking air through the opening at a second flow rate which is larger than the first flow rate; wherein while the blowing and suction steps are being simultaneously carried out, ambient air is permitted to enter the developer container through an ambient air inlet.

Abstract: A conveyor belt having a reinforcing layer of a synthetic fiber woven fabric embedded between an upper surface cover and a lower surface cover, wherein an elongation at break of the synthetic fiber woven fabric in a belt longitudinal direction is at least 25% and an elongation at a load 10% of a guarantee strength is not greater than 1.5%.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: A static electricity measuring system including a probe, a measuring device, and a calibration device. The probe includes a sensor which detects an electric field and outputs signals representing the detected electric field. The measuring device measures static electricity on the basis of the signals output from the sensor. The calibration device generates a reference electric field. The measuring device is adjusted when the sensor detects the reference electric field produced by the calibration device.