Patents by Inventor Thomas A. Figura
Thomas A. Figura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6667218Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.Type: GrantFiled: February 25, 1999Date of Patent: December 23, 2003Assignee: Micron Technology, Inc.Inventor: Thomas A. Figura
-
Patent number: 6664171Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.Type: GrantFiled: November 25, 2002Date of Patent: December 16, 2003Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Thomas A. Figura, J. Brett Rolfson
-
Patent number: 6645846Abstract: A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive structure. A third insulative material is deposited over the conductive structure and the sidewall etch stop. The third insulative material is different in composition from the second insulative material. A contact opening is etched through the third insulative material to the conductive structure using an etch chemistry which is substantially selective to the second insulative material of the sidewall etch stop. Integrated circuitry independent of the method of fabrication is disclosed.Type: GrantFiled: October 24, 2001Date of Patent: November 11, 2003Assignee: Micron Technology, Inc.Inventors: John M. Drynan, Thomas A. Figura
-
Publication number: 20030173565Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.Type: ApplicationFiled: March 14, 2003Publication date: September 18, 2003Applicant: Micron Technology, Inc.Inventors: Fernando Gonzalez, Thomas A. Figura, J. Brett Rolfson
-
Patent number: 6607966Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.Type: GrantFiled: January 2, 2002Date of Patent: August 19, 2003Assignee: Micron Technology, Inc.Inventors: Thomas A. Figura, Zhiqiang Wu, Li Li
-
Patent number: 6599840Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 29, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Patent number: 6596642Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Patent number: 6596648Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Publication number: 20030077913Abstract: A method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed in the substrate is hydrogen and optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be done after deposition of a metal layer, or at other process steps as desired.Type: ApplicationFiled: November 25, 2002Publication date: April 24, 2003Applicant: Micron Technology, Inc.Inventors: Fernando Gonzalez, Thomas A. Figura, J. Brett Rolfson
-
Publication number: 20030074787Abstract: A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive structure. A third insulative material is deposited over the conductive structure and the sidewall etch stop. The third insulative material is different in composition from the second insulative material. A contact opening is etched through the third insulative material to the conductive structure using an etch chemistry which is substantially selective to the second insulative material of the sidewall etch stop. Integrated circuitry independent of the method of fabrication is disclosed.Type: ApplicationFiled: October 24, 2001Publication date: April 24, 2003Inventors: John M. Drynan, Thomas A. Figura
-
Publication number: 20030075799Abstract: A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first insulative material. A second different insulative material is deposited. The second insulative material is anisotropically etched effective to form a sidewall etch stop for the conductive structure. A third insulative material is deposited over the conductive structure and the sidewall etch stop. The third insulative material is different in composition from the second insulative material. A contact opening is etched through the third insulative material to the conductive structure using an etch chemistry which is substantially selective to the second insulative material of the sidewall etch stop. Integrated circuitry independent of the method of fabrication is disclosed.Type: ApplicationFiled: October 3, 2002Publication date: April 24, 2003Inventors: John M. Drynan, Thomas A. Figura
-
Patent number: 6534335Abstract: A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.Type: GrantFiled: July 22, 1999Date of Patent: March 18, 2003Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Werner Juengling, Thomas A. Figura, Steven D. Cummings
-
Patent number: 6524875Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.Type: GrantFiled: December 11, 2001Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventors: Thomas A. Figura, Bradley J. Howard
-
Publication number: 20030017638Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.Type: ApplicationFiled: December 11, 2001Publication date: January 23, 2003Inventors: Thomas A. Figura, Bradley J. Howard
-
Patent number: 6507065Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughen ed inner and outer surfaces using ion implantation and an unplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughen ed by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughen ed outer surface to which has been transferred a near-impression image topography of the opposing inner surface.Type: GrantFiled: July 2, 2001Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventors: Thomas A. Figura, Zhiquiang Wu, Li Li
-
Publication number: 20020187648Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 12, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Publication number: 20020182816Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 5, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Publication number: 20020182872Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: ApplicationFiled: July 11, 2002Publication date: December 5, 2002Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Patent number: 6489219Abstract: An improved method for alloying a semiconductor substrate upon which wordlines enclosed in spacers have been formed, with the substrate exposed between the wordlines. A thin sealing layer is then deposited over the substrate and the wordlines, the sealing layer helping to maintain the alloy in said substrate. The alloying material employed of the substrate is optionally monatomic hydrogen. Alloying the substrate with monatomic hydrogen may also be used after deposition of a metal layer, or at other process steps as desired.Type: GrantFiled: November 9, 1995Date of Patent: December 3, 2002Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Thomas A. Figura, J. Brett Rolfson
-
Patent number: 6461967Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 16, 2001Date of Patent: October 8, 2002Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma