Abstract: A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming of an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective layer thereby forming exposed and covered regions of the protective layer. The exposed portions of the protective layer are removed to form at least first, second, and third disconnected protective structures, wherein the distance between the first and second protective structures is smaller than the distance between the second and third protective structures. The oxide layer and a portion of the substrate between the protective structures is removed to expose a portion of the substrate. A blanket polycrystalline silicon (poly) layer is formed over the substrate, and the poly layer is isotropically etched to remove the poly from between the second and third protective structures and leave a portion of the poly between the first and second structures.

Abstract: Polysilicon or amorphous silicon electrodes are selectively texturized with respect to neighboring dielectric surfaces. Selectivity of texturizing is partially accomplished by exploiting differences in seed incubation time on silicon as compared to neighboring surfaces. The texturizing process is made substantially completely selective by a texturizing post-etch, which selectively removes parasitic deposits from surfaces adjacent to the silicon electrodes. Selectively texturized electrodes represent a significant improvement in DRAM process integration.

Abstract: A capacitor apparatus includes, a) a substrate having a node; b) an inner capacitor plate in ohmic electrical connection with the substrate node; c) an outer capacitor plate; d) a capacitor dielectric layer interposed between inner and outer capacitor plates; e) an electrically conductive reaction barrier layer interposed between the substrate node and the inner capacitor plate, the reaction barrier layer having outer lateral edges which are recessed beneath the inner capacitor plate; and f) oxidation barrier blocks being received over the recessed outer lateral edges beneath the inner capacitor plate. Methods of forming such a capacitor are also disclosed.

Abstract: This invention is a process for fabricating a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate and a cell plate which covers both inner and outer surfaces of the storage-node plate. A plurality of oxide layers having alternately-varying composition are deposited on top of an in-process DRAM array to form a single sacrificial mold layer. In a preferred embodiment of the invention, ozone TEOS oxide is one of the alternately-varying layers, and plasma-enhanced TEOS oxide is the other. Ozone TEOS oxide etches more rapidly than does plasma-enhanced TEOS oxide, and both types of TEOS oxide are etchable with respect to polycrystalline silicon. Following the deposition of the sacrificial mold layer, the mold layer is patterned and anisotropically etched to form a mold opening in the mold layer. Contact to the storage node of the cell access transistor is made at the bottom of the mold opening.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxygen/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxide layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxide layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.

Abstract: A method of forming a capacitor apparatus includes providing a substrate having a node, providing an electrically conductive reaction barrier layer with opposed recessed lateral edges over the substrate node, forming an inner capacitor plate, providing oxidation barrier blocks over the opposed recessed lateral edges, forming a dielectric layer and providing an outer capacitor plate.

Abstract: This invention is a process for fabricating a dynamic random access memory (DRAM) having a stacked capacitor with hemispherical-grain (HSG) polysilicon asperities on an amorphous silicon storage-node plate. The process enables the selective formation of HSG polysilicon asperities on the storage-node plates and a subsequent deposition of a high-quality silicon nitride cell dielectric layer on the asperity-covered storage-node plates. The process is preferably initiated following field oxide formation, wordline formation, access transistor source/drain region formation, deposition of a planarizing dielectric layer, formation of bitline contact and storage-node contact openings in the planarizing layer, and formation of conductive plugs in both types of contact openings.

Abstract: A capacitor apparatus includes, a) a substrate having a node; b) an inner capacitor plate in ohmic electrical connection with the substrate node; c) an outer capacitor plate; d) a capacitor dielectric layer interposed between inner and outer capacitor plates; e) an electrically conductive reaction barrier layer interposed between the substrate node and the inner capacitor plate, the reaction barrier layer having outer lateral edges which are recessed beneath the inner capacitor plate; and f) oxidation barrier blocks being received over the recessed outer lateral edges beneath the inner capacitor plate. Methods of forming such a capacitor are also disclosed.

Abstract: A method of forming a contact area between two vertical structures. A first layer of material conforming to an extending between vertical sidewalls is covered with a mask layer. The mask layer is patterned and etched to remove the horizontal region of the mask layer between the vertical sidewalls, thereby exposing the first layer of material at the desired location of the contact area, while retaining at least a portion of the vertical regions of the mask layer. Using the remaining vertical regions of the mask layer as etch mask, the exposed portions of the first layer are then etched away to form the contact area. Another aspect of the invention provides a method of making a DRAM that utilizes a capacitor insulating layer over the capacitor second conductor (or cell poly) to self-align the bit line contact to the capacitor second conductor. In accordance with this aspect of the invention, a capacitor is formed over a semiconductor wafer.

Abstract: A process useful for isolating active areas of semiconductor devices in which an isolation trench is created in a substrate, the isolation trench being lined with an oxidation barrier and filled with a thick film. An oxidation step is performed in which the thick film is oxidized. The oxidation is self-limiting as the oxidation barrier prevents the substrate surrounding the trench from being oxidized.

Abstract: A capacitor apparatus includes, a) a substrate having a node; b) an inner capacitor plate in ohmic electrical connection with the substrate node; c) an outer capacitor plate; d) a capacitor dielectric layer interposed between inner and outer capacitor plates; e) an electrically conductive reaction barrier layer interposed between the substrate node and the inner capacitor plate, the reaction barrier layer having outer lateral edges which are recessed beneath the inner capacitor plate; and f) oxidation barrier blocks being received over the recessed outer lateral edges beneath the inner capacitor plate. Methods of forming such a capacitor are also disclosed.

Abstract: A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective layer thereby forming exposed and covered regions of the protective layer. The exposed portions of the protective layer are removed to form at least first, second, and third disconnected protective structures, wherein the distance between the first and second protective structures is smaller than the distance between the second and third protective structures. The oxide layer and a portion of the substrate between the protective structures is removed to expose a portion of the substrate. A blanket polycrystalline silicon (poly) layer is formed over the substrate, and the poly layer is isotropically etched to remove the poly from between the second and third protective structures and to leave a portion of the poly between the first and second structures.