Abstract: A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

Abstract: A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a substrate within a chemical vapor deposition reactor; b) chemical vapor depositing an in situ conductively doped amorphous silicon layer over the substrate within the reactor at a first temperature, the first temperature being below 600.degree. C., the doped amorphous silicon layer having an outer surface of a first degree of roughness; c) within the chemical vapor deposition reactor and after depositing the doped amorphous silicon layer, raising the substrate temperature at a selected rate to an annealing second temperature, the annealing second temperature being from 550.degree. C. to 950.degree. C.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: A process of forming a capacitor on a surface of a wafer having one or more word lines and an active area adjacent the word lines. The word lines are isolated from the active areas by isolation spacers. The process comprises the steps of forming a multilayer structure over the word lines and the active area, selectively removing a portion of the multilayer structure to expose active area and to form a capacitor container region above the active area and sequentially depositing the bottom electrode, the cell dielectric and the upper electrode of the capacitor. The multilayer structure comprises a conformal etch stop layer, a sacrificial layer and a mask layer. The etch stop layer protects the active area and word line spacers during a selective etch of the sacrificial layer, and the etch stop layer may then be removed with minimal damage to the gate electrode spacers. In the preferred embodiment, the process requires only two masking steps to form a fully isolated, high-surface area capacitor for a DRAM cell.

Abstract: Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF.sub.3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.

Abstract: A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

Abstract: Disclosed is an improved stacked capacitor with rounded corners for increasing capacitor breakdown voltage, and a method of constructing the same. The preferred method comprises rounding corners of a container-shaped bottom electrode. In particular, sharp corners of a pre-fabricated conductive silicon container are exposed to an ammonium hydroxide/peroxide mixture. The slow etching effect of the clean rounds angled surfaces thereby minimizing the high field effects usually associated with corners and other angled surfaces. Reducing such field effects by reducing or eliminating sharp corners helps prevent breakdown of the capacitor structure dielectric. When the conductive container includes a rough layer, such as hemispherical grained silicon, the invention provides the additional advantage of separating individual hemispherical grains, thus allowing later deposition of a uniformly thick dielectric layer.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxygen/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxide layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxide layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.

Abstract: A process for fabricating a recessed field oxide area comprises providing a substrate having isolation stacks and first and second recesses having openings therein, the first recesses being wider than the second recesses. The recesses can have a depth in the approximate range of 200.ANG.-3000.ANG.. Next, the first and second recesses are lined with nitride, and the substrate is blanketed with a conformal material which bridges the openings of the second recesses but not the openings of the first recesses. The conformal material and the nitride is removed from horizontal surfaces of the isolation stacks, and essentially all of the conformal material is removed from the first recesses. At least a portion of the conformal material is left in the second recesses. Subsequent to the step of removing the conformal material, the substrate and the conformal material is oxidized to create field oxide areas at the first and second recesses.

Abstract: A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.

Abstract: A method for forming a capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is LO deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxide/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxygen layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxygen layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains.

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a substrate within a chemical vapor deposition reactor; b) chemical vapor depositing an in situ conductively doped amorphous silicon layer over the substrate within the reactor at a first temperature, the first temperature being below 600.degree. C., the doped amorphous silicon layer having an outer surface of a first degree of roughness; c) within the chemical vapor deposition reactor and after depositing the doped amorphous silicon layer, raising the substrate temperature at a selected rate to an annealing second temperature, the annealing second temperature being from 550.degree. C. to 950.degree. C.

Abstract: Disclosed is an improved stacked capacitor with rounded corners for increasing capacitor breakdown voltage, and a method of constructing the same. The preferred method comprises rounding corners of a container-shaped bottom electrode. In particular, sharp corners of a pre-fabricated conductive silicon container are exposed to an ammonium hydroxide/peroxide mixture. The slow etching effect of the clean rounds angled surfaces thereby minimizing the high field effects usually associated with corners and other angled surfaces. Reducing such field effects by reducing or eliminating sharp corners helps prevent breakdown of the capacitor structure dielectric. Where the conductive container includes a rough layer, such as hemispherical grained silicon, the invention provides the additional advantage of separating individual hemispherical grains, thus allowing later deposition of a uniformly thick dielectric layer.

Abstract: A process for reducing stress during processing of semiconductor wafers comprising the steps of depositing a masking stack on a top and a bottom surface of the wafer and then removing at least a portion of the masking stack on the bottom surface prior to forming isolation regions on the top surface of the semiconductor wafer. In one embodiment, silicon nitride is formed on the top and the bottom surface of a silicon wafer. The silicon nitride is then patterned and etched on the top surface of the wafer to expose regions of the underlying silicon for field oxide formation. Prior to the field oxidation formation on the top side of the wafer, the silicon nitride layer on the bottom side of the wafer is removed so that a layer of silicon dioxide is formed on the bottom surface of the wafer during field oxidation formation.