Abstract: Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: A container capacitor having an elongated storage electrode for enhanced capacitance in a dynamic random access memory circuit. The electrode is preferably twice the length of the typical cell and may be coated with hemispherical-grain polysilicon to further increase the surface area of the electrode.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material.

Abstract: A process of forming a capacitor on a surface of a wafer having one or more word lines and an active area adjacent the word lines. The word lines are isolated from the active areas by isolation spacers. The process comprises the steps of forming a multilayer structure over the word lines and the active area, selectively removing a portion of the multilayer structure to expose active area and to form a capacitor container region above the active area and sequentially depositing the bottom electrode, the cell dielectric and the upper electrode of the capacitor. The multilayer structure comprises a conformal etch stop layer, a sacrificial layer and a mask layer. The etch stop layer protects the active area and word line spacers during a selective etch of the sacrificial layer, and the etch stop layer may then be removed with minimal damage to the gate electrode spacers. In the preferred embodiment, the process requires only two masking steps to form a fully isolated, high-surface area capacitor for a DRAM cell.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

Abstract: A silicon structure is formed that includes a free-standing wall having opposing roughened inner and outer surfaces using ion implantation and an unimplanted silicon etching process which is selective to implanted silicon. In general, the method provides a recess in a layer of insulating material into which a polysilicon layer is formed. A layer of HSG or CSG polysilicon is subsequently formed on the polysilicon layer, after which ions are implanted into both the layer of HSG or CSG polysilicon and the underlying polysilicon layer. The aforementioned selective etching process is then conducted to result in a relatively unimplanted portion being etched away and a highly implanted portion being left standing to form the free-standing wall. The free-standing wall has an inner surface that is roughened by the layer of HSG or CSG polysilicon. The free-standing wall also has a roughened outer surface to which has been transferred a near-impression image topography of the opposing inner surface.

Abstract: A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein.

Abstract: A method for forming HSG polysilicon with reduced dielectric bridging and increased capacitance. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is deposited at a reduced temperature to cause a nucleation of the second polysilicon layer. Grains are formed on the surface of the second polysilicon layer as a result of the nucleation. Next a wet etch is performed to remove portions of the polysilicon grains and portions of the first polysilicon layer. The duration of the wet etch is controlled to retain a roughened surface area. The size of the grains decreases during the wet etch and the distance between the grains increases. A dielectric layer is deposited to overlie the rough polysilicon following the wet etch. The thickness of the dielectric layer tends to be uniform thereby reducing bridging of the dielectric between the grains of the of the polysilicon.

Abstract: An improved method and structure which increases the alignment tolerances in multiple, singularized plugs are provided. The invention discloses a novel method for forming individual plug contacts with increased surface area for improved registration between semiconducting layers. Also the improved plug contacts are particularly well suited to receiving contact formations which have any taper to them. IGFETS and other devices formed from this design can be used in a variety of beneficial applications, e.g. logic or memory.