Patents by Inventor Thomas Andre

Thomas Andre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355456
    Abstract: A system includes a ranking engine (110) and a user interface (130). The ranking engine receives a list (114) for a patient which includes a plurality of occurrences (210) and computes a relevance score for each occurrence (210) in the list. The computed relevance score is according to a relevance scheme (116) that maps relevance scores from a lexicon controlling the list to each of the plurality of occurrences. The user interface (130) displays the list on a display device (137) of a local computing device (140) ordered by a presented computed relevance score that includes the computed relevance score. Each displayed occurrence of the plurality of occurrences includes a feedback indicator (136). The user interface receives feedback comprising an input for one displayed occurrence of the plurality of occurrences according to the feedback indicator which indicates the one displayed occurrence is to be displayed higher or lower in the list than a current position. The input is a binary indicator.
    Type: Application
    Filed: December 5, 2017
    Publication date: November 21, 2019
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Merlijn Sevenster, Thomas Andre Forsberg, Paul Joseph Chang
  • Patent number: 10446213
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 15, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Yaojun Zhang, Syed M. Alam, Thomas Andre
  • Publication number: 20190310981
    Abstract: In a tool for assisting in summarizing salient medical report findings, finding tokens (66) representing findings are extracted from a current medical report, and a salience value is computed for each such finding token based on statistics for the finding token in a reference database (32) including a count of reference medical reports of the containing the finding token in a report summary section and a count of reference medical reports containing the finding token anywhere in the report. A ranking or sub-set of findings extracted from the current medical report is displayed. The displayed findings may be ranked, or the sub-set chosen, by salience value. To generate the reference database, for each reference medical report (42) finding tokens (46) are extracted and it is determined whether each such finding token is salient based on whether the finding token is extracted from a report summary section of the reference report.
    Type: Application
    Filed: July 14, 2017
    Publication date: October 10, 2019
    Inventors: Merlijn Sevenster, Thomas Andre Forsberg
  • Publication number: 20190311810
    Abstract: The present disclosure pertains to a system configured to facilitate computational analysis of a health condition. In some embodiments, the system is configured to: obtain a graph comprising nodes and edges, the nodes comprising nodes of a first node type that correspond to risk parameters and nodes of a second node type that correspond to risk models; process the graph to generate a resulting graph for a first individual by: determining a value of a risk parameter of a first-type node (that has an edge linking the first-type node to a second-type node in the graph) with respect to the first individual; and removing edges linking the second-type node to first-type nodes from the graph based on the value of the risk parameter of the first-type node; and select, based on the resulting graph, risk models to be used to perform analysis of the first individual's health condition.
    Type: Application
    Filed: December 12, 2017
    Publication date: October 10, 2019
    Applicant: KONINKLIJKE PHILIPS N.V.
    Inventors: Merlijn SEVENSTER, Thomas Andre FORSBERG, Wilhelmus Johannes Allegonda Franciscus DIRKS
  • Publication number: 20190286305
    Abstract: A medical imaging system (100) includes a user interface (110) and a magnifying view engine (130). The user interface displays a view of a medical image on a display device (114) and to provide a moveable indicator (116) identifying a moveable point positioned in the displayed medical image. The magnifying view engine (130) generates a localized enlargement of a region of interest within the displayed medical image in response to selection of an existing end point or an existing contour in the displayed medical image according to a first input by one or more input devices and indicated by a current position of the moveable indicator.
    Type: Application
    Filed: September 26, 2017
    Publication date: September 19, 2019
    Inventors: Merlijn Sevenster, Thomas Andre Forsberg
  • Publication number: 20190287665
    Abstract: The present disclosure pertains to a medical summary interface view generation system. Medical reports are often verbose, and a specific user may only be interested in a fraction of the information conveyed in the report. Typical generation of a report summary is time consuming and laborious. The present system eases the creation of report summaries by automatically emphasizing and/or de-emphasizing items in a view of a medical report that might be of interest to the user according to pre-defined templates. This preserves control of what is included in the summary view while removing the laborious task of typing out a report summary from scratch.
    Type: Application
    Filed: October 6, 2017
    Publication date: September 19, 2019
    Inventors: Thomas Andre Forsberg, Merlijn Sevenster
  • Patent number: 10395699
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portion of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portions of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 27, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Publication number: 20190221247
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving a global word line to a first voltage. Driving the global word line to a first voltage results in a second voltage passed to the word lines. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 18, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190221242
    Abstract: The present disclosure is drawn to, among other things, a magnetic memory. The magnetic memory comprises a first common line, a second common line, and a memory cell. The magnetic memory further includes a bias voltage generation circuit and a voltage driver. The bias voltage generation circuit and the voltage driver are configured to provide driving voltages to the memory cell during access operations.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 18, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM, Frederick NEUMEYER
  • Publication number: 20190199375
    Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Syed M. ALAM, Thomas ANDRE
  • Patent number: 10304511
    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a first memory cell, a first clock-generating circuit, and a second clock-generating circuit. The first clock-generating circuit is configured to provide a first output signal and a second output signal. The second clock-generating circuit is configured to provide a third output signal and a fourth output signal. The first output signal, the second output signal, the third output signal, and the fourth output signal are configured for controlling access operations for the first memory cell.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 28, 2019
    Assignee: Everspin Technologies Inc.
    Inventors: Syed M. Alam, Yaojun Zhang, Thomas Andre
  • Publication number: 20190156878
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: December 12, 2018
    Publication date: May 23, 2019
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN
  • Publication number: 20190147971
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 16, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Publication number: 20190122192
    Abstract: In accordance with an embodiment, described herein is a system and method for orchestration of operations associated with a media content environment, including use of a prepare-proceed workflow process (workflow) that supports definition and use of different payment/billing systems or processes. A payment/billing server, for use with the media content environment dynamically generates workflows for use in processing payments associated with products. Upon receipt of a request to purchase a product, the payment/billing server generates a workflow to process a payment, including querying a product subsystem to determine pre-authorization steps required for purchase of the product and executing the pre-authorization steps; querying a transaction subsystem to determine a transaction information required for authorization; and querying a payment processor for authorization of the transaction.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 25, 2019
    Inventors: Thomas André Eriksson, Stefan Tom Ekerfelt
  • Patent number: 10268591
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 23, 2019
    Assignee: Everspin Technologies Inc.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
  • Patent number: 10269405
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
  • Patent number: 10256840
    Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Publication number: 20190087250
    Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Jon SLAUGHTER, Dimitri HOUSSAMEDDINE, Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190088306
    Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190043921
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Sanjeev AGGARWAL, Kerry Joseph NAGEL, Sarin A. DESHPANDE