Patents by Inventor Thomas Andre

Thomas Andre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetoresistive device design and process integration with surrounding circuitry
    Patent number: 9412786
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: August 9, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Self-referenced sense amplifier for spin-torque MRAM
    Patent number: 9401195
    Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: July 26, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • Method for writing to a magnetic tunnel junction device
    Patent number: 9378796
    Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 28, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Method of writing to a spin torque magnetic random access memory
    Patent number: 9378798
    Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 28, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft, Chitra Subramanian, Halbert Lin
  • WORD LINE AUTO-BOOTING IN A SPIN-TORQUE MAGNETIC MEMORY HAVING LOCAL SOURCE LINES
    Publication number: 20160180910
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Application
    Filed: February 29, 2016
    Publication date: June 23, 2016
    Inventors: Thomas Andre, Syed M. Alam
  • BOOSTED SUPPLY VOLTAGE GENERATOR FOR A MEMORY DEVICE AND METHOD THEREFORE
    Publication number: 20160172019
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Circuit and method for accessing a bit cell in a spin-torque MRAM
    Patent number: 9368181
    Abstract: Circuitry and a method for regulating voltages applied to magnetoresistive bit cells of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the ends of the selected bit cells are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The ends of the unselected bit cells are held at a precharge voltage while separately timed signals pull up or pull down the ends of the selected bit cells during read and write operations.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: June 14, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • NON-DESTRUCTIVE WRITE/READ LEVELING
    Publication number: 20160163371
    Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.
    Type: Application
    Filed: February 11, 2016
    Publication date: June 9, 2016
    Inventor: Thomas Andre
  • Boosted supply voltage generator for a memory device and method therefore
    Patent number: 9361964
    Abstract: A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 7, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • Nonvolatile logic and security circuits
    Patent number: 9336872
    Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 10, 2016
    Assignee: Everspin Technologies, Inc.
    Inventor: Thomas Andre
  • Memory Device With Timing Overlap Mode
    Publication number: 20160104518
    Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Inventors: Thomas Andre, Syed M. Alam, Halbert S. Lin
  • Word line supply voltage generator for a memory device and method therefore
    Patent number: 9311980
    Abstract: A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 12, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Dietmar Gogl, Syed M. Alam, Thomas Andre, Halbert S. Lin
  • METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
    Publication number: 20160099039
    Abstract: A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 7, 2016
    Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft, Chitra Subramanian, Halbert Lin
  • SELF-REFERENCED SENSE AMPLIFIER FOR SPIN TORQUE MRAM
    Publication number: 20160099040
    Abstract: Circuitry and a method provide a plurality of timed control and bias voltages to sense amplifiers and write drivers of a spin-torque magnetoresistive random access memory array for improved power supply noise rejection, increased sensing speed with immunity for bank-to-bank noise coupling, and reduced leakage from off word line select devices in an active column.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 7, 2016
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian
  • ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY
    Publication number: 20160092305
    Abstract: In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Syed M. Alam, Thomas Andre
  • WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE
    Publication number: 20160093349
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
  • MEMORY DEVICE WITH SHARED AMPLIFIER CIRCUITRY
    Publication number: 20160093341
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Inventors: Syed M. Alam, Thomas Andre
  • SHORT DETECTION AND INVERSION
    Publication number: 20160093354
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Hybrid read scheme for spin torque MRAM
    Patent number: 9299411
    Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 29, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Chitra Subramanian
  • EXPANDED ERROR CORRECTION CODES
    Publication number: 20160085622
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on whether the majority of bits are set to a high state or a low state. For instance, the memory device may be configured to set each bit in the memory array to a low state when the data is read. The memory device may then be configured to store the data in the original state when a majority of the bits to be written to the array are in the low state and in the inverted state when the majority of the bits to be written to the array are in the high state.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventor: Thomas Andre