Patents by Inventor Thomas Andre

Thomas Andre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190156878
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Application
    Filed: December 12, 2018
    Publication date: May 23, 2019
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas ANDRE, Dimitri HOUSSAMEDDINE, Syed M. ALAM, Jon SLAUGHTER, Chitra SUBRAMANIAN
  • Patent number: 10294304
    Abstract: The invention provides CARs (CARs) that specifically bind to BCMA (B-Cell Maturation Antigen). The invention further relates to engineered immune cells comprising such CARs, CAR-encoding nucleic acids, and methods of making such CARs, engineered immune cells, and nucleic acids. The invention further relates to therapeutic methods for use of these CARs and engineered immune cells for the treatment of a condition associated with malignant cells expressing BCMA (e.g., cancer).
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 21, 2019
    Assignee: Pfizer Inc.
    Inventors: Tracy Chia-Chien Kuo, Bijan Andre Boldajipour, Javier Fernando Chaparro Riggers, Philippe Duchateau, Roman Galetto, Alexandre Juillerat, Thomas Charles Pertel, Arvind Rajpal, Barbra Johnson Sasu, Cesar Adolfo Sommer, Julien Valton, Thomas John Van Blarcom
  • Publication number: 20190147971
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 16, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Publication number: 20190122192
    Abstract: In accordance with an embodiment, described herein is a system and method for orchestration of operations associated with a media content environment, including use of a prepare-proceed workflow process (workflow) that supports definition and use of different payment/billing systems or processes. A payment/billing server, for use with the media content environment dynamically generates workflows for use in processing payments associated with products. Upon receipt of a request to purchase a product, the payment/billing server generates a workflow to process a payment, including querying a product subsystem to determine pre-authorization steps required for purchase of the product and executing the pre-authorization steps; querying a transaction subsystem to determine a transaction information required for authorization; and querying a payment processor for authorization of the transaction.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 25, 2019
    Inventors: Thomas André Eriksson, Stefan Tom Ekerfelt
  • Patent number: 10268591
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 23, 2019
    Assignee: Everspin Technologies Inc.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
  • Patent number: 10269405
    Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Dimitri Houssameddine, Syed M. Alam, Jon Slaughter, Chitra Subramanian
  • Patent number: 10256840
    Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: April 9, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Publication number: 20190087250
    Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Jon SLAUGHTER, Dimitri HOUSSAMEDDINE, Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190088306
    Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.
    Type: Application
    Filed: November 15, 2018
    Publication date: March 21, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Syed M. ALAM
  • Publication number: 20190043921
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Application
    Filed: September 26, 2018
    Publication date: February 7, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas ANDRE, Sanjeev AGGARWAL, Kerry Joseph NAGEL, Sarin A. DESHPANDE
  • Patent number: 10199122
    Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Jon Slaughter, Dimitri Houssameddine, Syed M. Alam
  • Patent number: 10146601
    Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 4, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Jon Slaughter, Dimitri Houssameddine, Thomas Andre, Syed M. Alam
  • Patent number: 10141039
    Abstract: In some examples, a memory device is configured with a reduced command set and a variable burst length. In some instances, the variable burst length defines a page size associated with data to be loaded into a cache. In other instances, the variable burst length may be set on the fly per read/write command and, in some cases, the burst length may be utilized to define the page size associated with the read/write command.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 27, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam
  • Publication number: 20180322955
    Abstract: The present disclosure relates to visually indicating contributions of clinical risk factors to various model-based health assessments. In various embodiments, a plurality of clinical risk factors associated with a patient may be received and applied as input across a trained model to generate a score associated with the patient. Based on the trained model, first and second contributions of respective first and second clinical risk factors of the plurality of clinical risk factors to the score may be determined. A graphical user interface may be provided on a display, and the graphical user interface may include at least a first visual indication of the first contribution and a second visual indication of the second contribution.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 8, 2018
    Inventors: Merlijn Sevenster, Thomas Andre Forsberg
  • Patent number: 10114700
    Abstract: In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the memory also reads multiple pages of the internal page size from the memory array and stores them in the cache in response to receiving a single activate command.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 30, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • Patent number: 10109333
    Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: October 23, 2018
    Assignee: Everspin Technologies, Inc.
    Inventor: Thomas Andre
  • Patent number: 10103197
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: October 16, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Publication number: 20180267899
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 20, 2018
    Applicant: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Syed M. Alam, Chitra Subramanian, Javed S. Barkatullah
  • Publication number: 20180240537
    Abstract: A guided structured reporting apparatus (10) that enables clinicians to select report elements and generate a structured report (56), offering novel and improved structured reporting solutions that improves report (56) accuracy and precision, and expedites the generation of such a report (56). One or more processors (18) receive physiological information, generate a display, generate and display suggested finding codes (48) for adoption in the structured report (56), and generates and displays a structured report (56) based on the adopted finding codes (40).
    Type: Application
    Filed: March 9, 2016
    Publication date: August 23, 2018
    Inventors: MERLIJN SEVENSTER, THOMAS ANDRE FORSBERG
  • Patent number: 10037790
    Abstract: In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to reduce power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: July 31, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Thomas Andre, Syed M. Alam