Abstract: The present invention relates to a layer system (1) for thin-film solar cells with an absorber layer (4) that contains a chalcogenide compound semiconductor and a buffer layer (5) that is arranged on the absorber layer (4), wherein the buffer layer (5) contains NaxIn1SyClz with 0.05?x?0.2 or 0.2<x?0.5, 1?y?2, and 0.6?x/z?1.4.

Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

Abstract: The invention relates to a device for depositing a layer made of at least two components on an object, with a deposition chamber for disposing the object, at least one source with material to be deposited, as well as at least one device for controlling the deposition process, implemented such that the concentration of at least one component of the material to be deposited can be modified in its gas phase prior to deposition on the substrate by selective binding of a specified quantity of the at least one component, wherein the selectively bound quantity of the at least one component can be controlled by modifying at least one control parameter that is actively coupled to a binding rate or the component. It further relates to a device for depositing a layer made of at least two components on an object, wherein a device for controlling the deposition process has at least one gettering element made of a reactive material, wherein the reactive material includes copper and/or molybdenum.

Abstract: A memory cell includes a first electrode, a second electrode, a layer of phase change material extending from a first contact with the first electrode to a second contact with the second electrode, and a sidewall spacer contacting the second electrode and a sidewall of the layer of phase change material adjacent to the second contact.

Abstract: A solar module, more particularly a thin-film solar module having a plurality of solar cells connected in series for the photovoltaic generation of power, is described. The solar module has two voltage terminals of opposite polarity, which are each connected to an external surface of the module. Each of the two leads is electrically connected to a separate terminal device. Each of the two terminal housings is attached to the outer surface of the module. The two leads are electrically interconnected through a flyback diode, and the two terminal devices are electrically connected by a ribbon cable that is arranged between the two terminal housings and attached to the external surface of the module. A manufacturing method for the solar module is also described.

Abstract: A frameless solar module having a carrier substrate and a top layer connected thereto, between which there is a layer structure which forms a plurality of solar cells connected in series for the photovoltaic generation of power is described. The carrier substrate and/or the top layer of the frameless solar module is/are provided with mounting holes for mounting the solar module on a module bracket or for connection to at least one further solar module. The mounting holes are produced in a coating-free zone within a photovoltaically active region. Mounting arrangements having such a solar module which contain fixing elements which pass through the mounting holes are also described. Furthermore, a method for producing such a solar module in which the mounting holes are produced in the carrier substrate and/or in the top layer is also described.

Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.

Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.

Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

Abstract: A solar module having a connecting element is described. The solar module has a substrate, a back electrode layer, a photovoltaically active absorber layer, and a cover pane disposed one over the other, at least one prefabricated conductive film at least one connection housing.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.

Abstract: A device for depositing a layer containing at least two components on an object, including: a deposition chamber; a source containing a material to be deposited; and a control device, which controls the deposition process, implemented such that a concentration of the component of the material can be modified in its gas phase prior to deposition on the object by selective binding a specified quantity of the component, wherein the selectively bound quantity of the component is controlled by modifying a control parameter that is actively coupled to a binding rate or the component, and wherein the control device contains a gettering element containing a reactive material containing copper and/or molybdenum. Also, a method for depositing a layer containing at least two components on an object, wherein a selectively bound quantity of a component is controlled by modifying a binding rate of the component of the control device.

Abstract: A solar cell array is described which can be designed in particular as a thin-film solar module. A production method for a solar cell array is further described.

Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.

Abstract: According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.

Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.

Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.