Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8779495
    Abstract: An integrated circuit includes a first SONOS memory cell and a second SONOS memory cell. The second memory cell is stacked on the first memory cell.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: July 15, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8742387
    Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 3, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Franz Kreupl, Jan Boris Philipp, Petra Majewski
  • Publication number: 20140065787
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Application
    Filed: November 7, 2013
    Publication date: March 6, 2014
    Applicants: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Patent number: 8637844
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: January 28, 2014
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • Publication number: 20130319518
    Abstract: A solar module having a connecting element is described. The solar module has a substrate, a back electrode layer, a photovoltaically active absorber layer, and a cover pane disposed one over the other, at least one prefabricated conductive film at least one connection housing.
    Type: Application
    Filed: October 24, 2011
    Publication date: December 5, 2013
    Inventors: Matthias Doech, Christoph Degen, Robert Gass, Thomas Happ, Franz Karg, Lothar Lesmeister, Jan Boris Philipp, Mitja Rateiczak, Jaap Van Der Burgt, Andreas Schlarb, Bernhard Reul
  • Patent number: 8595449
    Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: November 26, 2013
    Assignee: Qimonda AG
    Inventors: Michael Kund, Thomas Happ, GillYong Lee, Heinz Hoenigschmid, Rolf Weis, Christoph Ludwig
  • Patent number: 8586960
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: November 19, 2013
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • Patent number: 8384062
    Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: February 26, 2013
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20130045558
    Abstract: A device for depositing a layer containing at least two components on an object, including: a deposition chamber; a source containing a material to be deposited; and a control device, which controls the deposition process, implemented such that a concentration of the component of the material can be modified in its gas phase prior to deposition on the object by selective binding a specified quantity of the component, wherein the selectively bound quantity of the component is controlled by modifying a control parameter that is actively coupled to a binding rate or the component, and wherein the control device contains a gettering element containing a reactive material containing copper and/or molybdenum. Also, a method for depositing a layer containing at least two components on an object, wherein a selectively bound quantity of a component is controlled by modifying a binding rate of the component of the control device.
    Type: Application
    Filed: February 22, 2011
    Publication date: February 21, 2013
    Applicant: Saint-Gobain Glass France
    Inventors: Joerg Palm, Stephan Pohlner, Stefan Jost, Thomas Happ
  • Publication number: 20120285512
    Abstract: A solar cell array is described which can be designed in particular as a thin-film solar module. A production method for a solar cell array is further described.
    Type: Application
    Filed: January 27, 2011
    Publication date: November 15, 2012
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 8284596
    Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 9, 2012
    Assignee: Qimonda AG
    Inventors: Igor Kasko, Thomas Happ, Andreas Walter, Stefan Tegen, Peter Baars, Klaus Muemmler
  • Patent number: 8250293
    Abstract: According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: August 21, 2012
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8208294
    Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8189372
    Abstract: An integrated circuit includes a first electrode including an etched recessed portion. The integrated circuit includes a second electrode and a resistivity changing material filling the recessed portion and coupled to the second electrode.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 29, 2012
    Assignees: International Business Machines Corporation, Macronix International Co., Ltd., Qimonda AG
    Inventors: Matthew Breitwisch, Shihhung Chen, Thomas Happ, Eric Joseph
  • Patent number: 8125006
    Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 28, 2012
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
  • Patent number: 8084799
    Abstract: A memory cell includes a first electrode, a second electrode, and phase change material between the first electrode and the second electrode. The phase change material has a step-like programming characteristic. The first electrode, the second electrode, and the phase change material form a via or trench memory cell.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: December 27, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 8039299
    Abstract: An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: October 18, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 8026123
    Abstract: The memory apparatus according to the invention and having a cell 14 has a high electrical resistance in a first state and a low electrical resistance in a second state. The cell 14 has an edge area 16 and a core area 15, in which the electrical resistivity in the edge area 16 is higher than in the core area 15 in the second state.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: September 27, 2011
    Assignee: Qimonda AG
    Inventor: Thomas Happ
  • Patent number: 8017930
    Abstract: A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: September 13, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 8009468
    Abstract: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 30, 2011
    Assignee: Qimonda AG
    Inventors: Dieter Andres, Thomas Happ, Petra Majewski, Bernhard Ruf