Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit including quench devices
    Patent number: 7889536
    Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit including memory cell having cup-shaped electrode interface
    Patent number: 7888665
    Abstract: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit for programming a memory cell
    Patent number: 7876606
    Abstract: An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit including a memory fabricated using self-aligned processing
    Patent number: 7875492
    Abstract: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Integrated circuit including diode memory cells
    Patent number: 7869257
    Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit including force-filled resistivity changing material
    Patent number: 7863593
    Abstract: An integrated circuit includes a first electrode, a second electrode, and force-filled resistivity changing material electrically coupled to the first electrode and the second electrode.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: January 4, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Energy adjusted write pulses in phase-change memory cells
    Patent number: 7859894
    Abstract: An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for at least some of the phase-change memory cells in accordance with the temperature sensed by the temperature sensor.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: December 28, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Zaidi Shoaib
  • Method for Fabricating an Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface
    Publication number: 20100323493
    Abstract: An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.
    Type: Application
    Filed: August 13, 2010
    Publication date: December 23, 2010
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Memory Including Vertical Bipolar Select Device and Resistive Memory Element
    Publication number: 20100321990
    Abstract: A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Multiple write configurations for a memory cell
    Patent number: 7852657
    Abstract: The present invention relates to a method of programming an array of memory cells such as phase change memory cells. In this method, a selection is made between a first pulse configuration and a second pulse configuration, wherein the first and second pulse configurations are different, and wherein each pulse configuration can write at least two data states to the memory cells of the array.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: December 14, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit including vertical diode
    Patent number: 7838860
    Abstract: An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 23, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • METHOD OF OPERATING AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT AND MEMORY MODULE
    Publication number: 20100293350
    Abstract: According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.
    Type: Application
    Filed: January 15, 2010
    Publication date: November 18, 2010
    Applicant: QIMONDA AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • RESISTIVE MEMORY CELL ACCESSED USING TWO BIT LINES
    Publication number: 20100290277
    Abstract: An integrated circuit includes a first bit line and a resistance changing memory element coupled to the first bit line. The integrated circuit includes a second bit line and a heater coupled to the second bit line. The integrated circuit includes an access device coupled to the resistance changing memory element and the heater.
    Type: Application
    Filed: January 22, 2010
    Publication date: November 18, 2010
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit including U-shaped access device
    Patent number: 7829879
    Abstract: An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: November 9, 2010
    Assignee: Qimonda AG
    Inventors: Rolf Weis, Thomas Happ
  • Method of fabricating an integrated circuit having a memory including a low-k dielectric material
    Patent number: 7824951
    Abstract: The present invention includes a memory cell device and method that includes a memory cell, a first electrode, a second electrode, phase-change material and an isolation material. The phase-change material is coupled adjacent the first electrode. The second electrode is coupled adjacent the phase-change material. The isolation material adjacent the phase-change material thermally isolates the phase-change material.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: November 2, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Shoaib Zaidi
  • Integrated circuit including resistivity changing material having a planarized surface
    Patent number: 7812333
    Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Integrated circuit including an array of memory cells and method
    Patent number: 7804708
    Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: September 28, 2010
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Lothar Risch, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
  • Resistive memory including buried word lines
    Patent number: 7800093
    Abstract: An integrated circuit including a memory cell includes a vertical bipolar select device including a base and an emitter. The memory cell includes a resistive memory element coupled to the emitter and a buried metallized word line contacting the base.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: September 21, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Memory device having drift compensated read operation and associated method
    Patent number: 7796424
    Abstract: A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memory cell. A method of reading a memory cell is also disclosed and includes detecting one or more drift conditions of a memory cell, and setting one or more read reference levels based on the one or more detected drift conditions. The memory cell is then read using the set one or more read reference levels.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 14, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Happ, Jan Boris Philipp
  • Optimized phase change write method
    Patent number: 7791933
    Abstract: A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark Lamorey, Thomas Happ