Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION
    Publication number: 20100032635
    Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 11, 2010
    Applicant: QIMONDA AG
    Inventors: Ulrike Gruening-von Schwerin, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
  • INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD
    Publication number: 20100027325
    Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 4, 2010
    Applicant: QIMONDA AG
    Inventors: Ulrike Gruening-von Schwerin, Lothar Risch, Peter Baars, Klaus Muemmler, Stefan Tegen, Thomas Happ
  • Integrated circuit for setting a memory cell based on a reset current distribution
    Patent number: 7646632
    Abstract: An integrated circuit includes an array of resistance changing memory cells and a first circuit. The first circuit is configured to set a selected memory cell to a crystalline state by applying a decreasing stair step pulse to the selected memory cell. The pulse is based on a reset current distribution for the array of memory cells.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 12, 2010
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Bernhard Ruf, Christian Rüster, Dieter Andres, Petra Majewski
  • Conditioning operations for memory cells
    Patent number: 7646625
    Abstract: One embodiment of the invention relates to a method for conditioning resistive memory cells of a memory array with a number of reliable resistance ranges, where each reliable resistance range corresponds to a different data state. In the method, group of at least one resistive memory cell is accessed, which group includes at least one unreliable cell. At least one pulse is applied to the at least one unreliable cell to shift at least one resistance respectively associated with the at least one unreliable cell to the highest of the reliable resistance ranges. Other methods and systems are also disclosed.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: January 12, 2010
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Thomas Nirschl
  • INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL
    Publication number: 20100002498
    Abstract: An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Applicant: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Resistive Memory Devices with Improved Resistive Changing Elements
    Publication number: 20090321706
    Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Applicant: QIMONDA AG
    Inventors: Thomas Happ, Franz Kreupl, Jan Boris Philipp, Petra Majewski
  • INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
    Publication number: 20090316473
    Abstract: An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 24, 2009
    Inventors: Thomas Happ, Hsiang-Lan Lung, Bipin Rajendran, Min Yang
  • INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE
    Publication number: 20090310401
    Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Applicant: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Bernhard Ruf, Christian Ruster
  • INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL
    Publication number: 20090303780
    Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 10, 2009
    Applicant: Qimonda AG
    Inventors: Igor Kasko, Thomas Happ, Andreas Walter, Stefan Tegen, Peter Baars, Klaus Muemmler
  • Integrated circuit having a precharging circuit
    Patent number: 7626858
    Abstract: A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: December 1, 2009
    Assignees: Qimonda North America Corp., Macronix International Co., Ltd.
    Inventors: Thomas Happ, Jan Boris Philipp, Ming-Hsiu Lee
  • Optimized phase change write method
    Patent number: 7626860
    Abstract: A method and system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC). The method and system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: December 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mark Lamorey, Thomas Happ
  • Phase Change Memory With Tapered Heater
    Publication number: 20090289242
    Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer. Another embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element.
    Type: Application
    Filed: July 29, 2009
    Publication date: November 26, 2009
    Applicant: International Business Machines Corporation
    Inventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
  • Semiconductor device including multi-bit memory cells and a temperature budget sensor
    Patent number: 7623401
    Abstract: One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares a first signal from the first temperature budget sensor to a first reference signal to obtain a first comparison result. The circuit refreshes the plurality of multi-bit memory cells based on the first comparison result.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: November 24, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • System that prevents reduction in data retention
    Patent number: 7619936
    Abstract: One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in back end processing from reducing data retention time of the configuration data in the resistive memory.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Memory cell with trigger element
    Patent number: 7619917
    Abstract: A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a trigger element.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 17, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Thomas Nirschl, Thomas Happ, Jan Boris Philipp
  • Integrated circuit having an insulated memory
    Patent number: 7615770
    Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material defines a narrow region. The memory cell includes first insulation material having a first thermal conductivity and contacting the phase-change material. A maximum thickness of the first insulation material contacts the narrow region. The memory cell includes a second insulation material having a second thermal conductivity greater than the first thermal conductivity and contacting the first insulation material.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventors: Jan Boris Philipp, Thomas Happ, Renate Bergmann
  • Integrated circuit having resistive memory cells
    Patent number: 7601995
    Abstract: A memory includes an array of memory cells, each memory cell including resistive material, a first insulation material laterally surrounding the resistive material of each memory cell, and a heat spreader between the memory cells to thermally isolate each memory cell.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: October 13, 2009
    Assignee: Infineon Technologies AG
    Inventors: Thomas Happ, Ulrike Gruening-von Schwerin, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL
    Publication number: 20090237983
    Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.
    Type: Application
    Filed: March 19, 2008
    Publication date: September 24, 2009
    Applicant: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Integrated circuit for programming a memory element
    Patent number: 7593255
    Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element by iteratively applying a variable program pulse to the memory element until a resistance of the memory element crosses a first reference resistance. The variable program pulse is adjusted for each iteration such that the resistance of the memory element approaches the first reference resistance.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 22, 2009
    Assignees: Qimonda North America Corp., Infineon Technologies AG
    Inventors: Thomas Happ, Thomas Nirschl, Jan Boris Philipp
  • INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
    Publication number: 20090206315
    Abstract: An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Applicant: Qimonda AG
    Inventors: Rolf Weis, Thomas Happ