Patents by Inventor Thomas Happ

Thomas Happ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8009468
    Abstract: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 30, 2011
    Assignee: Qimonda AG
    Inventors: Dieter Andres, Thomas Happ, Petra Majewski, Bernhard Ruf
  • Patent number: 8003971
    Abstract: An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 23, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Publication number: 20110198557
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 18, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, MACRONIX INTERNATIONAL CO., LTD., QIMONDA AG
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • Patent number: 7994536
    Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: August 9, 2011
    Assignee: Qimonda AG
    Inventors: Rolf Weis, Thomas Happ
  • Patent number: 7977661
    Abstract: An integrated circuit includes a bit line, a plurality of access devices coupled to the bit line, and a plate of phase change material. The integrated circuit includes a plurality of phase change elements contacting the plate of phase change material and a plurality of first contacts. Each first contact is coupled between an access device and a phase change element.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: July 12, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 7973301
    Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material including a first portion contacting the first electrode, a second portion contacting the second electrode, and a third portion between the first portion and the second portion. A width of the third portion is less than a width of the first portion and a width of the second portion.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: July 5, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Shoaib Hasan Zaidi, Jan Boris Philipp
  • Patent number: 7973384
    Abstract: A memory cell includes a first electrode, a second electrode, and a first portion of phase-change material contacting the first electrode. The memory cell includes a second portion of phase-change material contacting the second electrode and a third portion of phase-change material between the first portion and the second portion. A phase-change material composition of the third portion and the second portion gradually transitions from the third portion to the second portion.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: July 5, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7955958
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: June 7, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung, Min Yang
  • Patent number: 7939817
    Abstract: An integrated circuit includes a heater element serving as a first electrode, a second electrode, a memory element comprising resistance changing material coupled to the heater element and to the second electrode, and a diffusion compensation region coupled to the heater element and to the resistance changing material. The diffusion compensation region includes a surplus of at least one diffusible species present in the memory element and provides at least one diffusible species to the memory element.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 10, 2011
    Assignee: Qimonda AG
    Inventors: Dieter Andres, Thomas Happ, Petra Majewski, Bernhard Ruf
  • Patent number: 7932507
    Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: April 26, 2011
    Assignees: International Business Machines Corporation, Qimonda North America Corp., Macronix International Co., Ltd.
    Inventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
  • Patent number: 7929336
    Abstract: An integrated circuit includes a resistance changing memory element and a circuit. The circuit is configured to program the memory element to a crystalline state from an amorphous state by applying a seed pulse to the memory element followed by a set pulse.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: April 19, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ, Bernhard Ruf, Christian RĂ¼ster
  • Patent number: 7916524
    Abstract: A method of addressing a memory cell includes applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse. In addition, a memory includes a memory cell and a control circuit configured to address the memory cell by applying a plurality of pulses to the memory cell, wherein a subsequent pulse has an amplitude greater than an initial pulse.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 29, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7910911
    Abstract: An embodiment of the present invention includes a phase change memory (PCM) structure configurable for use as a nonvolatile storage element. The element includes at least one bottom electrode; at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; and at least one heater layer on at least a portion of an upper surface of the phase change material layer, wherein the heater layer has a tapered shape such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
  • Patent number: 7906368
    Abstract: An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Matthew Breitwisch, Thomas Happ, Eric A. Joseph, Hsiang-Lan Lung, Jan Boris Philipp
  • Patent number: 7902051
    Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including providing a single crystal substrate; forming an insulating layer on the single crystal substrate; forming a via through the insulating layer to provide an exposed portion of the single crystal substrate; forming amorphous Si on at least the exposed portion of the single crystal substrate; converting at least a portion of the amorphous Si into single crystal Si; and forming dopant regions in the single crystal Si. In one embodiment the diode of the present invention is integrated with a memory device.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: March 8, 2011
    Assignees: International Business Machines Corporation, Qimonda AG, Macronix International Co., Ltd.
    Inventors: Bipin Rajendran, Thomas Happ, Hsiang-Lan Lung
  • Patent number: 7888665
    Abstract: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7889536
    Abstract: An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: February 15, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp
  • Patent number: 7876606
    Abstract: An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 7875492
    Abstract: An integrated circuit includes transistors in rows and columns providing an array, conductive lines in columns across the array, and resistivity changing material elements contacting the conductive lines and self-aligned to the conductive lines. The integrated circuit includes electrodes contacting the resistivity changing material elements, each electrode self-aligned to a conductive line and coupled to one side of a source-drain path of a transistor.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Qimonda AG
    Inventors: Ulrike Gruening-von Schwerin, Thomas Happ
  • Patent number: 7869257
    Abstract: The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: January 11, 2011
    Assignee: Qimonda AG
    Inventors: Jan Boris Philipp, Thomas Happ