Abstract: One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.

Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

Abstract: An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.

Abstract: An integrated circuit includes a vertical diode defined by crossed line lithography.

Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

Abstract: An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode and the second electrode. The first resistivity changing material and the second resistivity changing material have different crystallization speeds.

Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.

Abstract: A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.

Abstract: An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.

Abstract: A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

Abstract: A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material has a step-like programming characteristic.

Abstract: A reprogrammable switch includes first phase-change material, a reference element, and a sense amplifier. The sense amplifier is coupled to the first phase-change material and the reference element and configured to compare a signal from the first phase-change material to a signal from the reference element and output a voltage signal based on the comparison.

Abstract: An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode.

Abstract: A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.

Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode.

Abstract: An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit includes first material between the sidewalls of the contact.

Abstract: An integrated circuit includes a first electrode and a cup-shaped electrode interface coupled to the first electrode. The integrated circuit includes a dielectric spacer at least partially laterally enclosed by the electrode interface and a resistance changing material laterally enclosed by the spacer and contacting the electrode interface. The integrated circuit includes a second electrode coupled to the resistance changing material.

Abstract: A memory cell includes a first electrode and an opposing second electrode, and a memory stack between the first and second electrodes. The memory stack includes a first layer of thermal isolation material contacting the first electrode, a second layer of thermal isolation material contacting the second electrode, and a phase change material between the first layer of thermal isolation material and the second layer of thermal isolation material. In this regard, the phase change material defines an active region width that is less than a width of either of the first layer of thermal isolation material and the second layer of thermal isolation material.