Patents by Inventor Thomas Langdo

Thomas Langdo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of producing high quality relaxed silicon germanium layers
    Patent number: 7674335
    Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Lattice-mismatched semiconductor structures on insulators
    Patent number: 7638842
    Abstract: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: December 29, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Zhiyuan Cheng, Thomas A. Langdo
  • Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
    Patent number: 7615829
    Abstract: A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: November 10, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Westhoff
  • Electronic Modules and Methods for Forming the Same
    Publication number: 20090250823
    Abstract: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 8, 2009
    Inventors: Livia M. Racz, Gary B. Tepolt, Jeffrey C. Thompson, Thomas A. Langdo, Andrew J. Mueller
  • INTERPOSERS, ELECTRONIC MODULES, AND METHODS FOR FORMING THE SAME
    Publication number: 20090250249
    Abstract: Electronic modules and interposers are formed by encapsulating microelectronic dies and/or posts within cavities in a substrate.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 8, 2009
    Inventors: Livia M. Racz, Gary B. Tepolt, Jeffrey C. Thompson, Thomas A. Langdo, Andrew J. Mueller
  • Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain
    Patent number: 7588994
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: September 15, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • LOW COST, HIGH-DENSITY RECTIFIER MATRIX MEMORY
    Publication number: 20090225579
    Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.
    Type: Application
    Filed: November 5, 2008
    Publication date: September 10, 2009
    Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
  • Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
    Patent number: 7439164
    Abstract: Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: October 21, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Anthony J. Lochtefeld
  • Strained-semiconductor-on-insulator device structures with elevated source/drain regions
    Patent number: 7420201
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: September 2, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Strained germanium-on-insulator device structures
    Patent number: 7414259
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: August 19, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • METHODS FOR FORMING III-V SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20080128751
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 5, 2008
    Applicant: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
    Publication number: 20070267722
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 22, 2007
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes
    Patent number: 7297612
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 20, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Strained-semiconductor-on-insulator device structures
    Patent number: 7259388
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: August 21, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Methods for integrating lattice-mismatched semiconductor structure on insulators
    Publication number: 20070054467
    Abstract: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew Currie, Anthony Lochtefeld, Zhiyuan Cheng, Thomas Langdo
  • Lattice-mismatched semiconductor structures on insulators
    Publication number: 20070054465
    Abstract: Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
    Type: Application
    Filed: September 7, 2005
    Publication date: March 8, 2007
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew Currie, Anthony Lochtefeld, Zhiyuan Cheng, Thomas Langdo
  • Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
    Publication number: 20060292719
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Application
    Filed: May 17, 2006
    Publication date: December 28, 2006
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony Lochtefeld, Matthew Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas Langdo
  • Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
    Publication number: 20060258125
    Abstract: Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
    Type: Application
    Filed: July 20, 2006
    Publication date: November 16, 2006
    Applicant: AmberWave Systems Corporation
    Inventors: Thomas Langdo, Anthony Lochtefeld
  • Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
    Patent number: 7122449
    Abstract: Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on the semiconductor substrate while in situ doping the epitaxial layer to suppress facet formation. Suppression of faceting during selective epitaxial growth by in situ doping of the epitaxial layer at a predetermined level rather than by manipulating spacer composition and geometry alleviates the stringent requirements on the device design and increases tolerance to variability during the spacer fabrication.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: October 17, 2006
    Assignee: Amberwave Systems Corporation
    Inventors: Thomas A. Langdo, Anthony J. Lochtefeld
  • Strained-semiconductor-on-insulator finFET device structures
    Patent number: 7109516
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 19, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Glyn Braithwaite, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald