Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.

Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.

Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.

Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.

Abstract: A delay line circuit includes a plurality of delay units configured to receive an input signal and to provide a first output signal. The plurality of delay units is configured to selectively invert or relay the input signal to produce the first output signal based on a first instruction received from a delay line controller. A phase interpolator unit includes an offset unit configured to selectively add a speed control unit in the phase interpolator unit based on a second instruction received from the delay line controller. The phase interpolator unit is further configured to receive the first output signal and provide a second output signal.

Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.

Abstract: A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode.

Abstract: A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.

Abstract: A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.

Abstract: A circuit comprises a first path, a second path, a current generating circuit, and a sense amplifier. The first path has a first current having a first current value. The second path has a second current having a second current value. The current generating circuit is configured to generate a reference current having a reference current value based on the first current value and the second current value. The sense amplifier is configured to receive a third current having a third current value and to generate a logical value based on the reference current value and the third current value.

Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

Abstract: A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating.

Abstract: A method includes receiving a first voltage at a first input circuit of a bi-directional charge pump circuit, selectively turning on a first switch of a switching circuit that is coupled electrically to a deep N-well transistor of a first set of one or more intermediate pump stages that are coupled between the first input circuit and a first output circuit, and providing a third voltage from the first output circuit in response to receiving a second voltage at an input of a first diode of the output circuit from the first set of the one or more intermediate pump stages.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.

Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.

Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

Abstract: A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), and is coupled to at least one capacitor, an input node, and an output node. The input node is arranged to receive an input signal. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the output node, and the DNW is arranged to float for a positive pump operation.

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.