Abstract: A method of determining the location of the breakdown in the gate oxide of a MOSFET is disclosed. Additionally, the method determines the location of the breakdown in a manner that is convenient to use and can be easily employed. The method will determine whether there is a breakdown in the gate oxide. If there is a breakdown, the method will enable determination of the location of the breakdown in the gate oxide.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin.

Abstract: A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms.

Abstract: A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.

Abstract: A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply.

Abstract: A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

Abstract: A flash memory microelectronic chip (1000) is formed with at least one integral test structure (100) for electrical measurement of transistor leakage current from the low voltage peripheral transistors. The invention is a very wide finger-type transistor (9, 10) with minimum channel length and a width of approximately 150,000 &mgr;m, equal to the estimated total width of the same type of periphery transistors in the chip circuit. One low voltage NMOS (9) and one low voltage PMOS finger-type transistor (10) allow monitoring of the standby current contribution from these two types of periphery transistors. Regular current or voltage tests can be applied to the test structure, thus providing information on the correlation of standby currents with single transistor off-state leakage currents.

Abstract: First and second dielectric constants, e1 and e2 respectively, for first and second dielectric materials forming a MOS (metal oxide semiconductor) stack are determined. First and second test MOS stacks having first and second total effective oxide thickness, EOTA and EOTB, respectively, are formed. The first and second test MOS stacks include first and second interfacial structures comprised of the second dielectric material with first and second thickness, T2A and T1A, respectively. In addition, the first and second test MOS stacks include first and second high-K structures comprised of the first dielectric material with first and second thickness, T2B and T1B, respectively. The thickness parameters EOTA, T1A, T2A, EOTB, T1B, and T2B of the test MOS stacks are measured. The dielectric constants, e1 and e2, are then determined depending on relations between values of EOTA, T1A, and T2A, and between values of EOTB, T1B, and T2B.

Abstract: System and method for determining a respective effective oxide thickness for each of first and second dielectric structures that form a MOS (metal oxide semiconductor) stack. A first plurality of test MOS (metal oxide semiconductor) stacks are formed, and each test MOS stack includes a respective first dielectric structure comprised of a first dielectric material and a respective second dielectric structure comprised of a second dielectric material. A respective deposition time for forming the respective first dielectric structure corresponding to each of the first plurality of test MOS stacks is varied such that a respective first effective oxide thickness of the respective first dielectric structure varies for the first plurality of test MOS stacks. A respective second effective oxide thickness of the respective second dielectric structure is maintained to be substantially same for each of the first plurality of test MOS stacks.