Abstract: A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith.

Abstract: Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.

Abstract: Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

Abstract: A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

Abstract: Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.

Abstract: A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

Abstract: One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell. Other methods and systems are also disclosed.

Abstract: A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith.

Abstract: A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

Abstract: An exemplary cascode amplifier circuit comprises a first intrinsic FET, a second intrinsic FET, a third intrinsic FET, and a fourth FET. The first intrinsic FET has a source connected to a target memory cell via a bit line and a drain connected to a first node. The second intrinsic FET has a gate connected to the source of the first intrinsic FET and a source connected to a reference voltage. The second intrinsic FET also has a drain connected at a second node to a gate of the first intrinsic FET. The third intrinsic FET has a source connected to the first node and a gate connected to a supply voltage, and further provides a load across the supply voltage and the first node. The fourth FET has a source connected to the second node and a drain connected to the supply voltage, the fourth FET having a gate connected to an input control voltage.

Abstract: A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Abstract: A method for fabricating a flash memory device by determining the active region width (10) of a semiconductor device (27) using a measuring technique for the source drain overdrive current elements (31, 32, 33) having different active region widths and using that difference to establish the difference between the active region width of the devices (31, 32, 33) and the drawn width and using the difference to establish the actual width (10) from drawn width in future devices, and a device thereby fabricated.

Abstract: An apparatus for measuring effects of isolation processes (280) on an oxide layer (286) in a memory device (255) is described. In one embodiment, the apparatus comprises a structure (110) comprised of an array (110c) of memory devices (255). A testing unit (120) is coupled with the structure (110). The testing unit (120) is for performing various electrical tests on the array (110c) of memory devices (255). The testing unit (120) is also for providing data regarding each memory device (255) in the array (110c) of memory devices (255). An analyzer (120) is coupled with the structure (110) for analyzing results of the various electrical tests. This determines the condition of the oxide layer (286) of each memory device (255) in the array of memory devices (110c).

Abstract: A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

Abstract: A method of generating an operating condition projection corresponding to a predetermined lifetime for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition by inducing a predetermined drain-source voltage for each stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Abstract: A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.

Abstract: A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

Abstract: A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current profile is recorded. A comparison of current profiles obtained for the two types of structures may indicate the presence and/or extent of STI corner effects. More specifically, a steeper slope for a normalized current versus time plot for an STI edge intensive structure (500) compared to a slope of a normalized plot of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness is observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

Abstract: A method of determining the active region width (10) of an active region (4) by measuring the respective gate currents (Ig,100, Ig,100′, Ig,100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element (16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective gate currents (Ig,100, Ig,100 ′, Ig,100″) as a quasi-linear function (IW) of the respective predetermined widths (Wi), extrapolating a calibration term (WI=0) from the quasi-linear function (IW), and subtracting the calibration term (WIg=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.