Abstract: The present disclosure relates to compositions including a plurality of steviol glycosides. The present disclosure also relates to sweetener compositions and sweetened compositions including a combination of steviol glycosides, and uses of such sweetener compositions to prepare sweetened compositions including food, beverages, dental products, pharmaceuticals, nutraceuticals, and the like.

Abstract: Example low latency tactile capacitive keyboards are disclosed. An example compute system includes a keyboard including a housing, a plurality of keys, and a touch sensor positioned between the housing and at least one of the plurality of keys, keyboard circuitry to detect a signal output by the touch sensor, the signal corresponding to a keystroke, and generate a code corresponding to the detected signal and processor circuitry to process the code to effect the keystroke.

Abstract: Sweetener compositions having particular glycoside compositions are described herein. The glycoside compositions include rebaudioside D and/or rebaudioside M that are combined with other glycosides such as rebaudioside E, rebaudioside G, rebaudioside N and/or rebaudioside O. The sweetener compositions can also include one or more bulking agents or other ingredients. The sweetener compositions can be used in foods and beverages.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.

Abstract: The present disclosure provides a monitoring device comprising a test composition, a test element comprising a test portion to which the test composition is releasably adhered, a detection reagent, and a container comprising a first end with an opening and a second end opposite the first end. The test composition comprises a predetermined quantity of tracer analyte. The container is configured to receive the test portion and configured to be operationally coupled to an analytical instrument. The tracer analyte and the detection reagent each are capable of participating in one or more chemical reaction that results in the formation of a detectable product. A method of using the monitoring device to assess the efficacy of a washing process is also provided.

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

Abstract: Suggested are surfactant compositions comprising: One or more alpha-sulfofatty acid disalts (A) of general formula (I), RICH (SO3M1) COOM2 (I), wherein the radical R 1 denotes a linear or branched alkyl or alkenyl radical having 6 to 18 C atoms and the radicals M 1 and M 2-independently of one another-are selected from the group H, Li, Na, K, Ca/2, Mg/2, Ammonium and alkanolamines and one or more polysaccharides (B) selected from the group consisting of dextrin and its derivatives, starch and its derivatives, cellulose and its derivatives, preferably one or more dextrins (B) of the general formula (II), (II) in which n is an integer between 3 and 200.

Abstract: The invention relates to the use of adsorb/desorb chromatography to prepare enriched compositions comprising rebaudioside B and/or rebaudioside D. Compositions with enriched rebaudioside-B and/or rebaudioside-D components may be prepared from Stevia-derived glycoside compositions using an adsorb-desorb chromatography process where the stationary phase of the chromatography bed comprises a macroporous neutral adsorbent resin.

Abstract: Novel steviol glycoside compounds characterized by a first group of four glucopyranose residues attached via the number 13 carbon (C13) of the steviol moiety and a second group of two or three glucopyranose residues attached via the number 19 carbon (C19) of the steviol moiety are described, and exemplified by compounds 1-4. These compounds can be present in a composition with other steviol glycosides (e.g., Reb D and Reb M) to enhance their solubilities. Accordingly, the novel compounds can facilitate the preparation of Compound name (C-13) aqueous compositions having a higher concentration of steviol glycosides. A steviol glycoside composition including one or more of compounds 1-4 can be used as a sweetener composition to sweeten other compositions (sweetenable compositions) such as foods, beverages, medicines, oral hygiene compositions, nutraceuticals, and the like.

Abstract: A server chassis includes a main frame, a fan module, and a flow-guiding device. The fan module and the flow-guiding device are in the main frame. The flow-guiding device includes a plurality of plate bodies. The plate bodies are parallel to each other and are spaced apart from each other by a spacing. Each of the plate bodies has a plurality of openings. The plurality of openings of one of the plate bodies are arranged alternately with those of another plate body adjacent to the one of the plate bodies.

Abstract: An electronic device is provided. The electronic device includes: a substrate, wherein the substrate has a normal direction; a first bonding pad and a second bonding pad disposed side by side on the substrate. The first bonding pad includes a first conductive layer and a second conductive layer, and the first conductive layer is adjacent to the second conductive layer. The second bonding pad includes a third conductive layer, the third conductive layer is adjacent to the second conductive layer, and in the normal direction, a distance between a bottom surface of the third conductive layer and the substrate is different than a distance between a bottom surface of the second conductive layer and the substrate. Viewed from the normal direction of the substrate, at least part of the second conductive layer is between the first conductive layer and the third conductive layer.

Abstract: The present disclosure provides a package device and a manufacturing method thereof. The package device includes a redistribution layer which includes a first dielectric layer, a conductive layer and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern that includes a first conductive pattern, and the first conductive pattern is formed of the conductive layer.

Abstract: A receiving circuit of a deserializer is provided. The receiving circuit of the deserializer receives an input signal and includes: a signal receiving terminal for receiving the input signal; a link equalizer circuit (LEQ) having a first input terminal coupled to the signal receiving terminal; and an out-of-band signaling (OOBS) circuit having a second input terminal coupled to the signal receiving terminal; a first resistor coupled between the signal receiving terminal and a first reference voltage; and a second resistor coupled between the signal receiving terminal and a second reference voltage; and a buffer circuit having a third input terminal and an output terminal, wherein the third input terminal receives a voltage, and the output terminal is coupled to the LEQ or the OOBS circuit. The first input terminal of the LEQ and the second input terminal of the OOBS circuit are not electrically coupled, and the voltage is adjustable.

Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.

Abstract: The present disclosure provides an electronic device including a substrate, a conductive pad, a chip and an insulating layer. The conductive pad is disposed on the substrate. The chip is disposed on the conductive pad. The insulating layer is disposed between the conductive pad and the chip, wherein the insulating layer includes an opening, and the chip is electrically connected to the conductive pad through the opening. An outline of the opening includes a plurality of curved corners in a normal direction of the substrate.

Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

Abstract: A method removes defects in a dielectric layer, such as during fabrication of a device that emits light from hot electrons injected into an atomically two-dimensional material. An atomically two-dimensional material and the dielectric layer are adjoined. The dielectric layer is adapted to convey a variable electric field for modulating a wavelength of photons electronically emitted across a band structure of the atomically two-dimensional material. Laser pulses are strobed into the dielectric layer with sufficient cumulative energy to remove a majority of the defects in the dielectric layer without altering the atomically two-dimensional material.

Abstract: A camera device includes an outer cap, a lens, a circuit board, and a dustproof sheet. The outer cap includes an axle hole, a first end, and a second end axially opposite to the first end. The lens is disposed on the first end of the outer cap. The circuit board is disposed on the second end of the outer cap. The circuit board includes an inner surface located in the axle hole. The inner surface has an optical sensing area and a non-optical sensing area. An optical sensing module is disposed on the optical sensing area to correspond to the lens. The dustproof sheet is disposed in the axle hole of the outer cap. The dustproof sheet covers the non-optical sensing area of the inner surface of the circuit board.

Abstract: The embodiments of the disclosure provide a manufacturing method of a package circuit, including the following steps. A circuit structure including a plurality of conductive pads is formed. A liquid crystal layer is formed on the circuit structure. An inspection step is performed, and the inspection step includes determining the conductivity of the conductive pads according to the result of the rotation of a liquid crystal layer oriented with an electric field. In addition, the liquid crystal layer is removed.

Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.